Rakesh Kumar
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Boomerang: A Metadata-Free Architecture for Control Flow Delivery
R Kumar, CC Huang, B Grot, V Nagarajan
High Performance Computer Architecture (HPCA), 2017 IEEE International …, 2017
362017
Blasting through the Front-End Bottleneck with Shotgun
R Kumar, B Grot, V Nagarajan
Proceedings of the Twenty-Third International Conference on Architectural …, 2018
302018
C 3 D: Mitigating the NUMA bottleneck via coherent DRAM caches
CC Huang, R Kumar, M Elver, B Grot, V Nagarajan
Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium …, 2016
212016
Dynamic selective devectorization for efficient power gating of SIMD units in a HW/SW co-designed environment
R Kumar, A Martínez, A González
Computer Architecture and High Performance Computing (SBAC-PAD), 2013 25th …, 2013
192013
DARCO: Infrastructure for Research on HW/SW co-designed Virtual Machines
D Pavlou, A Brankovic, R Kumar, M Gregori, K Stavrou, E Gibert, ...
Proceedings of the 4th Workshop on Architectural and Microarchitectural …, 2011
172011
Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment
R Kumar, A Martínez, A González
ACM Transactions on Architecture and Code Optimization (TACO) 11 (3), 25, 2014
162014
Freeway: Maximizing MLP for Slice-Out-of-Order Execution
R Kumar, M Alipour, D Black-Schaffer
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
122019
Speculative dynamic vectorization for HW/SW co-designed processors
R Kumar, A Martínez, A González
Proceedings of the 21st international conference on Parallel architectures …, 2012
102012
Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment
R Kumar, A Martínez, A González
ACM Transactions on Computer Systems (TOCS) 33 (4), 12, 2016
72016
Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment
R Kumar, A Martínez, A González
High Performance Computing (HiPC), 2013 20th International Conference on, 79-88, 2013
72013
Vectorizing for wider vector units in a HW/SW co-designed environment
R Kumar, A Martínez, A González
High Performance Computing and Communications & 2013 IEEE International …, 2013
72013
Delay and bypass: Ready and criticality aware instruction scheduling in out-of-order processors
M Alipour, S Kaxiras, D Black-Schaffer, R Kumar
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
62020
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
M Alipour, R Kumar, S Kaxiras, D Black-Schaffer
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 716-721, 2019
62019
HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation
R Kumar, J Cano, A Brankovicy, D Pavlouz, K Stavrouz, E Gibertx, ...
Performance Analysis of Systems and Software (ISPASS), 2017 IEEE …, 2017
32017
Quantitative characterization of the software layer of a HW/SW co-designed processor
J Cano, R Kumar, A Brankovic, D Pavlou, K Stavrouz, E Gibert, A Martınez, ...
Workload Characterization (IISWC), 2016 IEEE International Symposium on, 1-10, 2016
32016
Twig: Profile-Guided BTB Prefetching for Data Center Applications
TA Khan, N Brown, A Sriraman, N Soundararajan, R Kumar, J Devietti, ...
54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021
22021
Branch target buffer for a data processing apparatus
R Kumar, B Grot, V Nagarajan, CC Huang
22018
BTB-X: A Storage-Effective BTB Organization
T Asheim, B Grot, R Kumar
IEEE Computer Architecture Letters, 2021
12021
Branch target buffer arrangement for instruction prefetching
R Kumar, B Grot, V Nagarajan
US Patent App. 16/971,419, 2021
2021
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Cikkek 1–19