Követés
Rajit Manohar
Cím
Hivatkozott rá
Hivatkozott rá
Év
A million spiking-neuron integrated circuit with a scalable communication network and interface
PA Merolla, JV Arthur, R Alvarez-Icaza, AS Cassidy, J Sawada, ...
Science 345 (6197), 668-673, 2014
44022014
Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip
F Akopyan, J Sawada, A Cassidy, R Alvarez-Icaza, J Arthur, P Merolla, ...
IEEE transactions on computer-aided design of integrated circuits and …, 2015
16882015
A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm
P Merolla, J Arthur, F Akopyan, N Imam, R Manohar, DS Modha
Custom Integrated Circuits Conference (CICC), 2011 IEEE, 1-4, 2011
6012011
The Design of an Asynchronous MIPS R3000 Microprocessor
AJ Martin, A Lines, R Manohar, M Nyström, P Penzes, R Southworth, ...
Proceedings of the 17th Conference on Advanced Research in VLSI, 164-181, 1997
4481997
Braindrop: A mixed-signal neuromorphic architecture with a dynamical systems-based programming model
A Neckar, S Fok, BV Benjamin, TC Stewart, NN Oza, AR Voelker, ...
Proceedings of the IEEE 107 (1), 144-164, 2018
2392018
Highly pipelined asynchronous FPGAs
J Teifel, R Manohar
proceedings of the 2004 ACM/SIGDA 12th International symposium on field …, 2004
2362004
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core
JV Arthur, PA Merolla, F Akopyan, R Alvarez, A Cassidy, S Chandra, ...
the 2012 international joint conference on Neural networks (IJCNN), 1-8, 2012
1992012
Utilizing dynamically coupled cores to form a resilient chip multiprocessor
C LaFrieda, E Ipek, JF Martinez, R Manohar
37th Annual IEEE/IFIP International Conference on Dependable Systems and …, 2007
1912007
An asynchronous dataflow FPGA architecture
J Teifel, R Manohar
IEEE Transactions on Computers 53 (11), 1376-1392, 2004
1862004
Neuromorphic event-driven neural computing architecture in a scalable neural network
F Akopyan, JV Arthur, R Manohar, PA Merolla, DS Modha, A Molnar, ...
US Patent 8,909,576, 2014
1682014
An ultra low-power processor for sensor networks
V Ekanayake, C Kelly IV, R Manohar
ACM SIGOPS Operating Systems Review 38 (5), 27-36, 2004
1632004
A level-crossing flash asynchronous analog-to-digital converter
F Akopyan, R Manohar, AB Apsel
Asynchronous Circuits and Systems, 2006. 12th IEEE International Symposium …, 2006
1432006
Asynchronous analog-to-digital converter and method
F Akopyan, A Apsel, R Manohar
US Patent 7,466,258, 2008
1372008
Slack elasticity in concurrent computing
R Manohar, A Martin
Mathematics of Program Construction, 272-285, 1998
1151998
Real-time scalable cortical computing at 46 giga-synaptic OPS/watt with~ 100× speedup in time-to-solution and~ 100,000× reduction in energy-to-solution
AS Cassidy, R Alvarez-Icaza, F Akopyan, J Sawada, JV Arthur, ...
SC'14: Proceedings of the International Conference for High Performance …, 2014
1002014
Programmable asynchronous pipeline arrays
JR Teifel, R Manohar, Cornell Research Foundation, Inc., TC Jones, D Le
US Patent 7,157,934, 2007
932007
SNAP: A Sensor Network Asynchronous Processor
C Kelly, V Ekanayake, R Manohar
902003
Fault detection and isolation techniques for quasi delay-insensitive circuits
C LaFrieda, R Manohar
International Conference on Dependable Systems and Networks, 2004, 41-50, 2004
882004
Quasi-Delay-Insensitive Circuits are Turing-Complete
R Manohar, AJ Martin
CALIFORNIA INST OF TECH PASADENA DEPT OF COMPUTER, 1995
871995
Automated layout for integrated circuits with nonstandard cells
R Manohar, R Karmazin, CTO Otero
US Patent 9,852,253, 2017
842017
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