| Brisk and limited-impact NoC routing reconfiguration D Lee, R Parikh, V Bertacco 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 35 | 2014 |
| Highly fault-tolerant NoC routing with application-aware congestion management D Lee, R Parikh, V Bertacco Proceedings of the 9th International Symposium on Networks-on-Chip, 1-8, 2015 | 18 | 2015 |
| MTraceCheck: Validating non-deterministic behavior of memory consistency models in post-silicon validation D Lee, V Bertacco Proceedings of the 44th Annual International Symposium on Computer …, 2017 | 13 | 2017 |
| Low-overhead microarchitectural patching for multicore memory subsystems D Lee, O Matthews, V Bertacco 2018 IEEE 36th International Conference on Computer Design (ICCD), 17-25, 2018 | 7 | 2018 |
| Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification D Lee, T Kolan, A Morgenshtein, V Sokhin, R Morad, A Ziv, V Bertacco Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 6 | 2016 |
| VLSI implementation of a VC-1 main profile decoder for HD video applications J Cho, D Lee, S Yoon, S Park, SI Chae IEICE transactions on fundamentals of electronics, communications and …, 2009 | 2 | 2009 |
| Decompose and Conquer: Addressing Evasive Errors in Systems on Chip D Lee | 1 | 2018 |
| AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs B Mammo, D Lee, H Davis, Y Hou, V Bertacco 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 45-50, 2017 | 1 | 2017 |
| NoCVision: A network-on-chip dynamic visualization solution V Gogte, D Lee, R Parikh, V Bertacco Proceedings of the 8th International Workshop on Network on Chip …, 2015 | 1 | 2015 |
| Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms D Chatterjee, B Mammo, D Lee, R Gal, R Morad, A Nahir, A Ziv, ... 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 311-317, 2013 | 1 | 2013 |
| Bypassing Multicore Memory Bugs With Coarse-Grained Reconfigurable Logic D Lee, V Bertacco IEEE Transactions on Computers 71 (9), 2191-2204, 2021 | | 2021 |
| Test Generation and Lightweight Checking for Multi-core Memory Consistency D Lee, V Bertacco Post-Silicon Validation and Debug, 145-178, 2019 | | 2019 |
| A Hybrid Verification Methodology for SoCBase-DE Design Flow J Cho, D Lee, S Park, S Chae ITC-CSCC: International Technical Conference on Circuits Systems, Computers …, 2007 | | 2007 |
| Patching Design Flaws in Multicore Memory Subsystems D Lee, V Bertacco | | |
| ICCD 2018 D Lee, O Matthews | | |
| BugCalc: A Quantitative Evaluation of Bug Effects and Characteristics C Gao, CH Hsu, D Lee | | |
