Péter Szántó
Title
Cited by
Cited by
Year
Hierarchical Histogram-based Median Filter for GPUs
P Szántó, B Fehér
Acta Polytechnica Hungarica 15 (2), 2018
32018
Scalable architecture for rank order filtering
P Szántó, G Szedo, B Fehér, WC Chung
US Patent 8,005,881, 2011
32011
High Performance Timing-Driven Rank Filter
P Szántó, B Fehér, G Szedo
2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006
32006
High performance visibility testing with screen segmentation
P Szántó, B Fehér
2nd Workshop onEmbedded Systems for Real-Time Multimedia, 2004. ESTImedia …, 2004
22004
Scalable architecture for rank order filtering
P Szanto, G Szedo, B Feher, WC Chung
US Patent 8,713,082, 2014
12014
Accelerating virtual screening of compound libraries
P Szántó, B Fehér, A Bérces
Many-Core and Reconfigurable Supercomputing Conference (MRSC 09), 2009
12009
Implementing 2D median filter in FPGAs
P Szántó, G Szedő, B Fehér
Vysoká škola báňská-Technická univerzita Ostrava, 2006
12006
Exact Bucket Sorting for Segmented Screen Rendering
P Szántó, B Fehér
GSPX, 2005
12005
A Springer iPhone alkalmazása
S Péter
Tudományos és Műszaki Tájékoztatás 59 (10), 447, 2012
2012
FPGA implementation of cheminformatics and computational chemistry algorithms and its cost/performance comparison with GPGPU, cloud computing and SIMD implementations
A Berces, B Feher, P Szanto, I Pechan, L Lajko, Z Runyo, P Laczko, ...
ABSTRACTS OF PAPERS OF THE AMERICAN CHEMICAL SOCIETY 240, 2010
2010
Scalable architecture for rank order filtering
P Szanto, G Szedo, B Feher, W C. Chung
2007
Antialiasing IN Segmented Rendering
P SZÁNTÓ
13TH PHD MINI-SYMPOSIUM, 10, 2006
2006
3D RENDERING: SEGMENTED SCREEN IMAGE PROCESSING
P SZÁNTÓ
12TH PHD MINI-SYMPOSIUM, 14, 2005
2005
Péter Szántó, András Széll, Béla Fehér: Accelerating SOLiD short read assembly with GPU (download PDF)
P Szántó, G Szedő
2005
3D rendering using FPGAs.
P Szántó, B Fehér
VLSI-SOC, 149-154, 2003
2003
Accelerating SOLiD short read assembly with GPU
P Szántó, B Fehér, A Széll
High Performance Multi-Channel DMA Controller for FPGA Based Embedded Systems
P Szántó
REGIONAL CONFERENCE ON EMBEDDED AND AMBIENT SYSTEMS, 24, 0
3D RENDERING: MINIMIZING THE OVERHEAD OF NON-VISIBLE PIXELS
P SZÁNTÓ
Implementing a Programmable Pixel Pipeline in FPGAs
P Szántó, B Fehér
Hardware Implementation of a Programmable Pixel Pipeline
P Szántó, B Fehér
Scalable Rasterizer Unit
P Szántó, B Fehér
Sborník vědeckých prací Vysoké školy báňské-Technické univerzity Ostrava
P SZÁNTÓ, G SZEDŐ, B FEHÉR
Efficient and Scalable 3D Rendering Architecture
P Szántó, B Fehér
EFFICIENT MULTI-CHANNEL FIR FILTERS IN FPGA
P SZÁNTÓ, J LAZÁNYI, B FEHÉR
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