| Next generation spin torque memories BK Kaushik, S Verma, AA Kulkarni, S Prajapati Springer, 2017 | 24 | 2017 |
| Spintronics-based devices to circuits: Perspectives and challenges S Verma, AA Kulkarni, BK Kaushik IEEE Nanotechnology Magazine 10 (4), 13-28, 2016 | 23 | 2016 |
| Novel 4F2 Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device S Verma, S Kaundal, BK Kaushik IEEE Transactions on Nanotechnology 13 (6), 1163-1171, 2014 | 22 | 2014 |
| Modeling of a magnetic tunnel junction for a multilevel STT-MRAM cell S Prajapati, S Verma, AA Kulkarni, BK Kaushik IEEE Transactions on Nanotechnology 18, 1005-1014, 2018 | 16 | 2018 |
| Low-power high-density STT MRAMs on a 3-D vertical silicon nanowire platform S Verma, BK Kaushik IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (4 …, 2015 | 15 | 2015 |
| Spin Transfer Torque (STT) Based Devices, Circuits, and Memory SV Brajesh Kumar Kaushik ARTECH HOUSE 1, 302, 2016 | 13 | 2016 |
| Non-volatile latch compatible with static and dynamic CMOS for logic in memory applications S Verma, R Paul, M Shukla IEEE Transactions on Magnetics 58 (4), 1-8, 2022 | 9 | 2022 |
| All spin logic: A micromagnetic perspective S Verma, MS Murthy, BK Kaushik IEEE Transactions on Magnetics 51 (10), 1-10, 2015 | 8 | 2015 |
| Modeling of in-plane magnetic tunnel junction for mixed mode simulations S Verma, S Kaundal, BK Kaushik IEEE Transactions on Magnetics 50 (8), 1-7, 2014 | 8 | 2014 |
| Optimal Boolean Logic Quantum Circuit Decomposition for Spin-Torque-Based -Qubit Architecture A Kulkarni, S Prajapati, S Verma, BK Kaushik IEEE Transactions on Magnetics 54 (10), 1-9, 2018 | 7 | 2018 |
| Performance Enhancement of STT MRAM Using Asymmetric-Sidewall-Spacer NMOS S Verma, PK Pal, S Mahawar, BK Kaushik IEEE Transactions on Electron Devices 63 (7), 2771-2776, 2016 | 7 | 2016 |
| Area-efficient auto-write-terminate circuit for NV latch and logic-in-memory applications J Rajpoot, S Verma IEEE Transactions on Circuits and Systems II: Express Briefs 70 (7), 2630-2634, 2023 | 4 | 2023 |
| Low power STT MRAM cell with asymmetric drive current vertical GAA select device S Verma, S Mahawar, BK Kaushik 2015 12th International Conference on Electrical Engineering/Electronics …, 2015 | 4 | 2015 |
| SPICE Based Compact Model for Voltage-induced Magnetocapacitance in Magnetic Tunnel Junctions J Rajpoot, R Paul, S Verma IEEE Transactions on Magnetics, 2023 | 3 | 2023 |
| FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance Enhancement R Singh, S Verma, S Mittal IEEE Transactions on Electron Devices 69 (12), 6699-6704, 2022 | 3 | 2022 |
| Next generation 3-D spin transfer torque magneto-resistive random access memories BK Kaushik, S Verma, AA Kulkarni, S Prajapati, BK Kaushik, S Verma, ... Next Generation Spin Torque Memories, 13-34, 2017 | 2 | 2017 |
| Magnetic Domain Wall Race Track Memory BK Kaushik, S Verma, AA Kulkarni, S Prajapati, BK Kaushik, S Verma, ... Next Generation Spin Torque Memories, 71-92, 2017 | 2 | 2017 |
| Novel compact model for multi-level spin torque magnetic tunnel junctions S Prajapati, S Verma, AA Kulkarni, BK Kaushik Spintronics IX 9931, 84-92, 2016 | 2 | 2016 |
| Design space exploration and power optimization of STT MRAM using trimmed fin Asymmetric FinFET A Kumar, J Rajpoot, S Verma Microelectronics Journal 149, 106238, 2024 | 1 | 2024 |
| Emerging Memory Technologies BK Kaushik, S Verma, AA Kulkarni, S Prajapati, BK Kaushik, S Verma, ... Next Generation Spin Torque Memories, 1-12, 2017 | 1 | 2017 |
Brajesh Kumar KaushikProfessor of Electronics and Communication Engg., IIT-RoorkeeVerified email at iitr.ac.in
