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Vassos Soteriou
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A statistical traffic model for on-chip interconnection networks
V Soteriou, H Wang, L Peh
14th IEEE International Symposium on Modeling, Analysis, and Simulation, 104-116, 2006
2152006
Design-space exploration of power-aware on/off interconnection networks
V Soteriou, LS Peh
IEEE International Conference on Computer Design: VLSI in Computers and …, 2004
1492004
Exploring the design space of self-regulating power-aware on/off interconnection networks
V Soteriou, LS Peh
IEEE Transactions on Parallel and Distributed Systems 18 (3), 393-408, 2007
1122007
Dynamic power management for power optimization of interconnection networks using on/off links
V Soteriou, LS Peh
11th Symposium on High Performance Interconnects, 2003. Proceedings., 15-20, 2003
1102003
Design of a high-throughput distributed shared-buffer NoC router
RS Ramanujam, V Soteriou, B Lin, LS Peh
2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, 69-78, 2010
1022010
A high-throughput distributed shared-buffer NoC router
V Soteriou, RS Ramanujam, B Lin, LS Peh
IEEE Computer Architecture Letters 8 (1), 21-24, 2009
782009
Software-directed power-aware interconnection networks
V Soteriou, N Eisley, LS Peh
ACM Transactions on Architecture and Code Optimization (TACO) 4 (1), 5-es, 2007
742007
Software-directed power-aware interconnection networks
V Soteriou, N Eisley, LS Peh
Proceedings of the 2005 ACM International Conference on Compilers …, 2005
742005
Up by their bootstraps: Online learning in artificial neural networks for CMP uncore power management
JY Won, X Chen, P Gratz, J Hu, V Soteriou
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
682014
Intelligent hotspot prediction for network-on-chip-based multicore systems
E Kakoulli, V Soteriou, T Theocharides
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
602012
Polaris: A system-level roadmap for on-chip interconnection networks
V Soteriou, N Eisley, H Wang, B Li, LS Peh
2006 International Conference on Computer Design, 134-141, 2006
602006
Use it or lose it: Wear-out and lifetime in future chip multiprocessors
H Kim, A Vitkovskiy, PV Gratz, V Soteriou
Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013
552013
High-level power analysis for multi-core chips
N Eisley, V Soteriou, LS Peh
Proceedings of the 2006 international conference on Compilers, architecture …, 2006
452006
A dynamically adjusting gracefully degrading link-level fault-tolerant mechanism for NoCs
A Vitkovskiy, V Soteriou, C Nicopoulos
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
352012
Extending the effective throughput of nocs with distributed shared-buffer routers
RS Ramanujam, V Soteriou, B Lin, LS Peh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
332011
Virtualizing virtual channels for increased network-on-chip robustness and upgradeability
M Evripidou, C Nicopoulos, V Soteriou, J Kim
2012 IEEE Computer Society Annual Symposium on VLSI, 21-26, 2012
312012
Polaris: A system-level roadmapping toolchain for on-chip interconnection networks
V Soteriou, N Eisley, H Wang, B Li, LS Peh
IEEE transactions on very large scale integration (VLSI) systems 15 (8), 855-868, 2007
272007
Hermes: Architecting a top-performing fault-tolerant routing algorithm for Networks-on-Chips
C Iordanou, V Soteriou, K Aisopos
2014 IEEE 32nd International Conference on Computer Design (ICCD), 424-431, 2014
262014
A fine-grained link-level fault-tolerant mechanism for networks-on-chip
A Vitkovskiy, V Soteriou, C Nicopoulos
2010 IEEE International Conference on Computer Design, 447-454, 2010
232010
Fault adaptive routing in metasurface controller networks
T Saeed, C Skitsas, D Kouzapas, M Lestas, V Soteriou, A Philippou, ...
2018 11th International Workshop on Network on Chip Architectures (NoCArc), 1-6, 2018
202018
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Articles 1–20