| Optimizing FPGA-based accelerator design for deep convolutional neural networks C Zhang, P Li, G Sun, Y Guan, B Xiao, J Cong Proceedings of the 2015 ACM/SIGDA international symposium on field …, 2015 | 1915 | 2015 |
| A novel architecture of the 3D stacked MRAM L2 cache for CMPs G Sun, X Dong, Y Xie, J Li, Y Chen 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 515 | 2009 |
| Caffeine: Toward uniformed representation and acceleration for deep convolutional neural networks C Zhang, G Sun, Z Fang, P Zhou, P Pan, J Cong IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 511 | 2018 |
| Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement X Dong, X Wu, G Sun, Y Xie, H Li, Y Chen 2008 45th ACM/IEEE Design Automation Conference, 554-559, 2008 | 399 | 2008 |
| FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates Y Guan, H Liang, N Xu, W Wang, S Shi, X Chen, G Sun, W Zhang, J Cong 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017 | 267 | 2017 |
| Emerging non-volatile memories: Opportunities and challenges CJ Xue, Y Zhang, Y Chen, G Sun, JJ Yang, H Li Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011 | 223 | 2011 |
| An efficient design and implementation of LSM-tree based key-value store on open-channel SSD P Wang, G Sun, S Jiang, J Ouyang, S Lin, C Zhang, J Cong Proceedings of the Ninth European Conference on Computer Systems, 1-14, 2014 | 201 | 2014 |
| An efficient design and implementation of LSM-tree based key-value store on open-channel SSD P Wang, G Sun, S Jiang, J Ouyang, S Lin, C Zhang, J Cong Proceedings of the Ninth European Conference on Computer Systems, 1-14, 2014 | 201 | 2014 |
| Energy-efficient CNN implementation on a deeply pipelined FPGA cluster C Zhang, D Wu, J Sun, G Sun, G Luo, J Cong Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | 196 | 2016 |
| Energy-and endurance-aware design of phase change memory caches Y Joo, D Niu, X Dong, G Sun, N Chang, Y Xie 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 188 | 2010 |
| FPGA-based accelerator for long short-term memory recurrent neural networks Y Guan, Z Yuan, G Sun, J Cong 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 629-634, 2017 | 183 | 2017 |
| A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement G Sun, Y Joo, Y Chen, Y Chen, Y Xie Emerging memory technologies, 51-77, 2014 | 175 | 2014 |
| Adaptive placement and migration policy for an STT-RAM-based hybrid cache Z Wang, DA Jiménez, C Xu, G Sun, Y Xie 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 141 | 2014 |
| Coordinated static and dynamic cache bypassing for GPUs X Xie, Y Liang, Y Wang, G Sun, T Wang 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 138 | 2015 |
| Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation T Zhang, K Chen, C Xu, G Sun, T Wang, Y Xie 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014 | 133 | 2014 |
| Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs AK Mishra, X Dong, G Sun, Y Xie, N Vijaykrishnan, CR Das 2011 38th Annual International Symposium on Computer Architecture (ISCA), 69-80, 2011 | 123 | 2011 |
| An efficient compiler framework for cache bypassing on GPUs X Xie, Y Liang, G Sun, D Chen 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 516-523, 2013 | 108 | 2013 |
| Joint task assignment, transmission, and computing resource allocation in multilayer mobile edge computing systems P Wang, C Yao, Z Zheng, G Sun, L Song IEEE Internet of Things Journal 6 (2), 2872-2884, 2018 | 104 | 2018 |
| Graphh: A processing-in-memory architecture for large-scale graph processing G Dai, T Huang, Y Chi, J Zhao, G Sun, Y Liu, Y Wang, Y Xie, H Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 103 | 2018 |
| Multi-level cell STT-RAM: Is it realistic or just a dream? Y Zhang, L Zhang, W Wen, G Sun, Y Chen 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 526-532, 2012 | 101 | 2012 |
Yuan XieProfessor of University of California at Santa BarbaraVerified email at ece.ucsb.edu
