Kyle Rupnow
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FPGA/DNN co-design: An efficient design methodology for IoT intelligence on the edge
C Hao, X Zhang, Y Li, S Huang, J Xiong, K Rupnow, W Hwu, D Chen
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
Improving high level synthesis optimization opportunity through polyhedral transformations
W Zuo, Y Liang, P Li, K Rupnow, D Chen, J Cong
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013
High-level synthesis: productivity, performance, and software constraints
Y Liang, K Rupnow, Y Li, D Min, MN Do, D Chen
Journal of Electrical and Computer Engineering 2012, 1-1, 2012
Efficient GPU spatial-temporal multitasking
Y Liang, HP Huynh, K Rupnow, RSM Goh, D Chen
IEEE Transactions on Parallel and Distributed Systems 26 (3), 748-760, 2014
High-performance video content recognition with long-term recurrent convolutional network for FPGA
X Zhang, X Liu, A Ramachandran, C Zhuge, S Tang, P Ouyang, Z Cheng, ...
2017 27th International Conference on Field Programmable Logic and …, 2017
SkyNet: a hardware-efficient method for object detection and tracking on embedded systems
X Zhang, H Lu, C Hao, J Li, B Cheng, Y Li, K Rupnow, J Xiong, T Huang, ...
Proceedings of Machine Learning and Systems 2, 216-229, 2020
Machine Learning on FPGAs to Face the IoT Revolution
X Zhang, A Ramachandran, C Zhuge, D He, W Zuo, Z Cheng, K Rupnow, ...
ICCAD, 2017
Hardware acceleration of the pair-HMM algorithm for DNA variant calling
S Huang, GJ Manikandan, A Ramachandran, K Rupnow, WW Hwu, ...
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
High Level Synthesis of Complex Applications: An H. 264 Video Decoder
X Liu, Y Chen, T Nguyen, S Gurumani, K Rupnow
Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs
D Chen, J Cong, S Gurumani, W Hwu, K Rupnow, Z Zhang
IET Cyber‐Physical Systems: Theory & Applications 1 (1), 70-77, 2016
High Level Synthesis of Stereo Matching: Productivity, Performance, and Software Constraints
K Rupnow, Y Liang, Y Li, D Min, M Do, D Chen
Field Programmable Technology, 2011
A study of high-level synthesis: Promises and challenges
K Rupnow, Y Liang, Y Li, D Chen
2011 9th IEEE International Conference on ASIC, 1102-1105, 2011
An accurate GPU performance model for effective control flow divergence optimization
Z Cui, Y Liang, K Rupnow, D Chen
2012 IEEE 26th International Parallel and Distributed Processing Symposium …, 2012
A Real-Time 3D Sound Localization System with Miniature Microphone Array for Virtual Reality
S Zhao, S Ahmed, Y Liang, K Rupnow, D Chen, DL Jones
Industrial Electronics and Applications (ICIEA), 7th IEEE Conference on …, 2012
Block, drop or roll (back): Alternative preemption methods for RH multi-tasking
K Rupnow, W Fu, K Compton
Field Programmable Custom Computing Machines, 2009. FCCM'09. 17th IEEE …, 2009
Fast and effective placement and routing directed high-level synthesis for FPGAs
H Zheng, ST Gurumani, K Rupnow, D Chen
Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014
High-Level Synthesis With Behavioral-Level Multicycle Path Analysis
H Zheng, ST Gurumani, L Yang, D Chen, K Rupnow
Field Programmable Logic, 1 - 8, 2013
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
Y Chen, ST Gurumani, Y Liang, G Li, D Guo, K Rupnow, D Chen
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1 - 14, 2015
High-Level Synthesis of Multiple Dependent CUDA Kernels on FPGA
ST Gurumani, H Cholakkal, Y Liang, K Rupnow, D Chen
ASP-DAC, 2013
Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs
Y Liang, Z Cui, S Zhao, K Rupnow, Y Zhang, DL Jones, D Chen
Design Automation and Test in Europe, 2012
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