| DATA – Differential Address Trace Analysis: Finding Address-based Side-Channels in Binaries S Weiser, A Zankl, R Spreitzer, K Miller, S Mangard, G Sigl 27th USENIX Security Symposium (USENIX Security 18), 2018 | 70 | 2018 |
| {AutoLock}: Why cache attacks on {ARM} are harder than you think M Green, L Rodrigues-Lima, A Zankl, G Irazoqui, J Heyszl, T Eisenbarth 26th USENIX Security Symposium (USENIX Security 17), 1075-1091, 2017 | 61 | 2017 |
| PerfWeb: How to violate web privacy with hardware performance events B Gulmezoglu, A Zankl, T Eisenbarth, B Sunar Computer Security–ESORICS 2017: 22nd European Symposium on Research in …, 2017 | 47 | 2017 |
| How to break secure boot on fpga socs through malicious hardware N Jacob, J Heyszl, A Zankl, C Rolfes, G Sigl Cryptographic Hardware and Embedded Systems–CHES 2017: 19th International …, 2017 | 45 | 2017 |
| Towards protected MPSoC communication for information protection against a malicious NoC J Sepúlveda, A Zankl, D Flórez, G Sigl Procedia computer science 108, 1103-1112, 2017 | 39 | 2017 |
| Undermining user privacy on mobile devices using AI B Gulmezoglu, A Zankl, MC Tol, S Islam, T Eisenbarth, B Sunar Proceedings of the 2019 ACM Asia Conference on Computer and Communications …, 2019 | 20 | 2019 |
| Automated detection of instruction cache leaks in modular exponentiation software A Zankl, J Heyszl, G Sigl Smart Card Research and Advanced Applications: 15th International Conference …, 2017 | 18 | 2017 |
| Exploiting bus communication to improve cache attacks on systems-on-chips J Sepulveda, M Gross, A Zankl, G Sigl 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 284-289, 2017 | 17 | 2017 |
| Earthquake—A NoC-based optimized differential cache-collision attack for MPSoCs C Reinbrecht, B Forlin, A Zankl, J Sepúlveda 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 648-653, 2018 | 16 | 2018 |
| Breaking trustzone memory isolation through malicious hardware on a modern fpga-soc M Gross, N Jacob, A Zankl, G Sigl Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware …, 2019 | 15 | 2019 |
| Side-channel attacks in the Internet of Things: threats and challenges A Zankl, H Seuschek, G Irazoqui, B Gulmezoglu Research Anthology on Artificial Intelligence Applications in Security, 2058 …, 2021 | 13 | 2021 |
| Compromising FPGA SoCs using malicious hardware blocks N Jacob, C Rolfes, A Zankl, J Heyszl, G Sigl Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 12 | 2017 |
| Cache attacks and countermeasures for ntruencrypt on mpsocs: Post-quantum resistance for the iot J Sepulveda, A Zankl, O Mischke 2017 30th IEEE International System-on-Chip Conference (SOCC), 120-125, 2017 | 9 | 2017 |
| Beyond cache attacks: Exploiting the bus-based communication structure for powerful on-chip microarchitectural attacks J Sepúlveda, M Gross, A Zankl, G Sigl ACM Transactions on Embedded Computing Systems (TECS) 20 (2), 1-23, 2021 | 7 | 2021 |
| Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC M Gross, N Jacob, A Zankl, G Sigl Journal of Cryptographic Engineering, 1-16, 2022 | 6 | 2022 |
| Automated detection of instruction cache leaks in rsa software implementations A Zankl, J Heyszl, G Sigl Smart Card Research and Advanced Applications: 15th International Conference …, 2016 | 5 | 2016 |
| Towards efficient evaluation of a time-driven cache attack on modern processors A Zankl, K Miller, J Heyszl, G Sigl Computer Security–ESORICS 2016: 21st European Symposium on Research in …, 2016 | 5 | 2016 |
| Minimizing the costs of side-channel analysis resistance evaluations in early design steps T Korak, T Plos, A Zankl 2013 International Conference on Availability, Reliability and Security, 169-177, 2013 | 4 | 2013 |
| Towards trace-driven cache attacks on Systems-on-Chips—exploiting bus communication J Sepulveda, M Gross, A Zankl, G Sigl 2017 12th International Symposium on Reconfigurable Communication-centric …, 2017 | 1 | 2017 |
| EGIS NoC: A secure-enhanced interconnection to prevent Architectural Channel Attacks C Reinbrecht, B Forlin, A Zankl, J Sepulveda Testmethoden und Zuverlässigkeit von Schaltungen und Systemen,{TUZ} 2018, 2018 | | 2018 |
Martha Johanna Sepúlveda FlórezSenior Scientist Secure Communication, AIRBUS Defence and SpaceVerified email at airbus.com
