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Ioannis (Yannis) Schoinas
Ioannis (Yannis) Schoinas
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Title
Cited by
Cited by
Year
Intel Virtualization Technology for Directed I/O.
D Abramson, J Jackson, S Muthrasanallur, G Neiger, G Regnier, ...
Intel technology journal 10 (3), 2006
3882006
Fine-grain access control for distributed shared memory
I Schoinas, B Falsafi, AR Lebeck, SK Reinhardt, JR Larus, DA Wood
Proceedings of the sixth international conference on Architectural support …, 1994
3791994
Fine-grain access control for distributed shared memory
I Schoinas, B Falsafi, AR Lebeck, SK Reinhardt, JR Larus, DA Wood
Proceedings of the sixth international conference on Architectural support …, 1994
3791994
Application-specific protocols for user-level shared memory
B Falsafi, AR Lebeck, SK Reinhardt, I Schoinas, MD Hill, JR Larus, ...
Supercomputing'94: Proceedings of the 1994 ACM/IEEE Conference on …, 1994
2281994
Application-specific protocols for user-level shared memory
B Falsafi, AR Lebeck, SK Reinhardt, I Schoinas, MD Hill, JR Larus, ...
Supercomputing'94: Proceedings of the 1994 ACM/IEEE Conference on …, 1994
2281994
Application-specific protocols for user-level shared memory
B Falsafi, AR Lebeck, SK Reinhardt, I Schoinas, MD Hill, JR Larus, ...
Supercomputing'94: Proceedings of the 1994 ACM/IEEE Conference on …, 1994
2281994
Integration Challenges and Tradeoffs for Tera-scale Architectures.
M Azimi, N Cherukuri, DN Jayasimha, A Kumar, P Kundu, S Park, ...
Intel technology journal 11 (3), 2007
1242007
Address translation for input/output devices using hierarchical translation tables
I Schoinas, R Madukkarumakumana, G Neiger, R Uhlig, K King
US Patent 7,444,493, 2008
1222008
Address translation for input/output devices using hierarchical translation tables
I Schoinas, R Madukkarumakumana, G Neiger, R Uhlig, K King
US Patent 7,444,493, 2008
1222008
Resource partitioning and direct access utilizing hardware support for virtualization
RS Madukkarumukumana, G Neiger, I Schoinas
US Patent 7,467,381, 2008
1052008
Relaxed consistency and coherence granularity in DSM systems: A performance evaluation
Y Zhou, L Iftode, JP Sing, K Li, BR Toonen, I Schoinas, MD Hill, DA Wood
Proceedings of the sixth ACM SIGPLAN Symposium on Principles and Practice of …, 1997
1011997
Performance enhancement of address translation using translation tables covering large address spaces
I Schoinas, G Neiger, R Madukkarumukumana, K King, R Uhlig, AR Zahir, ...
US Patent 8,843,727, 2014
1002014
Performance enhancement of address translation using translation tables covering large address spaces
I Schoinas, G Neiger, R Madukkarumukumana, K King, R Uhlig, AR Zahir, ...
US Patent 8,843,727, 2014
1002014
Performance enhancement of address translation using translation tables covering large address spaces
I Schoinas, G Neiger, R Madukkarumukumana, K King, R Uhlig, AR Zahir, ...
US Patent 8,843,727, 2014
1002014
Interrupt redirection for virtual partitioning
RS Madukkarumukumana, I Schoinas, G Neiger
US Patent 7,222,203, 2007
962007
Caching support for direct memory access address translation
I Schoinas, R Madukkarumukumana, G Neiger, R Uhlig, B Vembu
US Patent 7,334,107, 2008
892008
Caching support for direct memory access address translation
I Schoinas, R Madukkarumukumana, G Neiger, R Uhlig, B Vembu
US Patent 7,334,107, 2008
892008
Synchronizing memory copy operations with memory accesses
S Ramakrishnan, I Schoinas
US Patent 7,127,566, 2006
892006
Synchronizing memory copy operations with memory accesses
S Ramakrishnan, I Schoinas
US Patent 7,127,566, 2006
892006
Performing memory RAS operations over a point-to-point interconnect
S Ramakrishnan, I Schoinas
US Patent 7,127,567, 2006
802006
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