| Bitslice implementation of AES C Rebeiro, D Selvakumar, ASL Devi Cryptology and Network Security: 5th International Conference, CANS 2006 …, 2006 | 104 | 2006 |
| Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs C Rebeiro, SS Roy, D Mukhopadhyay Cryptographic Hardware and Embedded Systems–CHES 2012: 14th International …, 2012 | 81 | 2012 |
| High speed compact elliptic curve cryptoprocessor for FPGA platforms C Rebeiro, D Mukhopadhyay Progress in Cryptology-INDOCRYPT 2008: 9th International Conference on …, 2008 | 63 | 2008 |
| Theoretical modeling of elliptic curve scalar multiplier on LUT-based FPGAs for area and speed SS Roy, C Rebeiro, D Mukhopadhyay IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (5), 901-909, 2012 | 62 | 2012 |
| Shakti-t: A risc-v processor with light weight security extensions A Menon, S Murugan, C Rebeiro, N Gala, K Veezhinathan Proceedings of the Hardware and Architectural Support for Security and …, 2017 | 53 | 2017 |
| Revisiting the Itoh-Tsujii inversion algorithm for FPGA platforms C Rebeiro, SS Roy, DS Reddy, D Mukhopadhyay IEEE Transactions on very large scale integration (vlsi) systems 19 (8 …, 2010 | 48 | 2010 |
| XFC: a framework for exploitable fault characterization in block ciphers P Khanna, C Rebeiro, A Hazra Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 34 | 2017 |
| Cache timing attacks on Clefia C Rebeiro, D Mukhopadhyay, J Takahashi, T Fukunaga Progress in Cryptology-INDOCRYPT 2009: 10th International Conference on …, 2009 | 33 | 2009 |
| Timing channels in cryptography: a micro-architectural perspective C Rebeiro, D Mukhopadhyay, S Bhattacharya Springer, 2014 | 31 | 2014 |
| PARAM: A microprocessor hardened for power side-channel attack resistance MA KF, V Ganesan, R Bodduna, C Rebeiro 2020 IEEE International Symposium on Hardware Oriented Security and Trust …, 2020 | 29 | 2020 |
| Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER R Bodduna, V Ganesan, P Slpsk, K Veezhinathan, C Rebeiro IEEE Computer Architecture Letters 19 (1), 9-12, 2020 | 29 | 2020 |
| Power attack resistant efficient FPGA architecture for Karatsuba multiplier C Rebeiro, D Mukhopadhyay 21st International Conference on VLSI Design (VLSID 2008), 706-711, 2008 | 29 | 2008 |
| PERI: A configurable posit enabled risc-V core S Tiwari, N Gala, C Rebeiro, V Kamakoti ACM Transactions on Architecture and Code Optimization (TACO) 18 (3), 1-26, 2021 | 28* | 2021 |
| Theoretical modeling of the Itoh-Tsujii inversion algorithm for enhanced performance on k-LUT based FPGAs SS Roy, C Rebeiro, D Mukhopadhyay 2011 Design, Automation & Test in Europe, 1-6, 2011 | 28 | 2011 |
| Pinpointing cache timing attacks on AES C Rebeiro, M Mondal, D Mukhopadhyay 2010 23rd International Conference on VLSI Design, 306-311, 2010 | 26 | 2010 |
| Karna: A gate-sizing based security aware EDA flow for improved power side-channel attack protection P Slpsk, PK Vairam, C Rebeiro, V Kamakoti 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 25 | 2019 |
| Cryptanalysis of CLEFIA Using Differential Methods with Cache Trace Patterns. C Rebeiro, D Mukhopadhyay CT-RSA 6558, 89-103, 2011 | 25 | 2011 |
| Boosting profiled cache timing attacks with a priori analysis C Rebeiro, D Mukhopadhyay IEEE Transactions on Information Forensics and Security 7 (6), 1900-1905, 2012 | 24 | 2012 |
| ProBLeSS: A proactive blockchain based spectrum sharing protocol against SSDF attacks in cognitive radio IoBT networks M Patnaik, G Prabhu, C Rebeiro, V Matyas, K Veezhinathan IEEE Networking Letters 2 (2), 67-70, 2020 | 21 | 2020 |
| DRECON: DPA resistant encryption by construction S Hajra, C Rebeiro, S Bhasin, G Bajaj, S Sharma, S Guilley, ... Progress in Cryptology–AFRICACRYPT 2014: 7th International Conference on …, 2014 | 21 | 2014 |
Debdeep MukhopadhyayProfessor, Dept of Computer Science and Engineering, IIT Kharagpur, IndiaVerified email at cse.iitkgp.ac.in
