A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element V Dhanasekaran, M Gambhir, MM Elsayed, E Sánchez-Sinencio, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 132 | 2009 |
A Continuous Time Multi-BitADC Using Time Domain Quantizer and Feedback Element V Dhanasekaran, M Gambhir, MM Elsayed, E Sanchez-Sinencio, ... IEEE Journal of Solid-State Circuits 46 (3), 639-650, 2011 | 73 | 2011 |
A low THD, low power, high output-swing time-mode-based tunable oscillator via digital harmonic-cancellation technique MM Elsayed, E Sanchez-Sinencio IEEE Journal of Solid-State Circuits 45 (5), 1061-1071, 2010 | 72 | 2010 |
A spur-frequency-boosting PLL with a− 74 dBc reference-spur suppression in 90 nm digital CMOS MM Elsayed, M Abdul-Latif, E Sanchez-Sinencio IEEE Journal of Solid-State Circuits 48 (9), 2104-2117, 2013 | 46 | 2013 |
A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Modulator MM Elsayed, V Dhanasekaran, M Gambhir, J Silva-Martinez, ... IEEE Journal of Solid-State Circuits 46 (9), 2084-2098, 2011 | 37 | 2011 |
A Wideband Millimeter-Wave Frequency Synthesis Architecture Using Multi-Order Harmonic-Synthesis and Variable-Push Frequency Multiplication MM Abdul-Latif, MM Elsayed, E Sanchez-Sinencio IEEE journal of solid-state circuits 46 (6), 1265-1283, 2011 | 32 | 2011 |
Method and apparatus for calibration of successive approximation register analog-to-digital converters Y Zhou, C Daigle, S Yan, M Elsayed US Patent 9,041,569, 2015 | 25 | 2015 |
High speed low current voltage comparator NM Atkinson, P Kallam, MM Elsayed US Patent 9,866,215, 2018 | 16 | 2018 |
System and method for correcting offset voltage errors within a band gap circuit M Elsayed, SD Willingham US Patent 10,310,528, 2019 | 11 | 2019 |
New applications and technology scaling driving next generation A/D converters H Zhang, MM Elsayed, E Sanchez-Sinencio 2009 European Conference on Circuit Theory and Design, 109-112, 2009 | 9 | 2009 |
A Spur-Frequency-Boosting PLL with a− 74dBc reference-spur rejection in 90nm digital CMOS M Elsayed, M Abdul-Latif, E Sánchez-Sinencio 2011 IEEE Radio Frequency Integrated Circuits Symposium, 1-4, 2011 | 6 | 2011 |
Slew-rate controlled supply voltage switching MM Elsayed, KW Fernald, M Powell US Patent 10,468,983, 2019 | 5 | 2019 |
Bias Current Generator MM Elsayed, MM Elkholy US Patent App. 15/609,644, 2018 | 5 | 2018 |
Clocked reference buffer in a successive approximation analog-to-digital converter M Elsayed, X Wang, S Yan US Patent 8,922,418, 2014 | 5 | 2014 |
Pixel ramp generator for image sensor M Elsayed, M Powell, X Wang US Patent 11,303,293, 2022 | 3 | 2022 |
Apparatus for sensing temperature in electronic circuitry and associated methods MM Elsayed, KW Fernald US Patent 10,788,376, 2020 | 3 | 2020 |
Current steering architecture with high supply noise rejection M Elsayed US Patent 11,363,228, 2022 | 1 | 2022 |
Reduced-leakage apparatus for sampling electrical signals and associated methods MM Elsayed US Patent 11,264,111, 2022 | 1 | 2022 |
Loadable true-single-phase-clocking flop M Elsayed US Patent 11,095,275, 2021 | 1 | 2021 |
Apparatus with electronic circuitry having reduced leakage current and associated methods MM Elsayed US Patent 10,659,045, 2020 | 1 | 2020 |