Muhammad Yasin

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Ozgur SinanogluProfessor of Electrical and Computer Engineering, New York University Abu DhabiVerified email at nyu.edu
Jeyavijayan (JV) RajendranAssociate Professor of Electrical and Computer Engineering, Texas A&M UniversityVerified email at tamu.edu
Bodhisatwa MazumdarAssociate Professor, Department of Computer Science and Engineering, Indian Institute of TechnologyVerified email at iiti.ac.in
Abhrajit Sengupta (অভ্রজিৎ সেনগুপ্ত)Senior Engineer, QualcommVerified email at qti.qualcomm.com
Mohammed Nabeel Thari MoopanResearch Engineer, DFX lab, NYUADVerified email at nyu.edu
Lilas AlrahisPostdoctoral Associate, New York University, Abu DhabiVerified email at nyu.edu
Ramesh Karri కర్రి రమేష్Professor of Electrical and Computer Engineering, New York UniversityVerified email at nyu.edu
Yiorgos MakrisThe University of Texas at DallasVerified email at utdallas.edu
Nimisha Limaye, Ph.D.Sr. Security IP Engineer @ Synopsys | NYUVerified email at nyu.edu
Nithyashankari G JayasankaranSoC Security Architect at QualcommVerified email at qti.qualcomm.com
M. Saquib SarfrazMercedes-Benz / Karlsruhe Institute of Technology (KIT)Verified email at mercedes-benz.com
Samah Mohamed A. SaeedAssistant Professor of Electrical Engineering, City College, City University of New YorkVerified email at ccny.cuny.edu
Mohammed IsmailProfessor and Chair, Electrical and Computer Engineering Department, Wayne State UniversityVerified email at wayne.edu
Haralampos-G. StratigopoulosSorbonne Université, CNRS, LIP6Verified email at lip6.fr
Zhaokun HanPhD student, Texas A&M UniversityVerified email at tamu.edu
Ibrahim (Abe) M ElfadelProfessor, Khalifa University, Abu Dhabi, UAEVerified email at ku.ac.ae

Muhammad Yasin

National University of Sciences & Technology, Pakistan

Verified email at nyu.edu

Hardware Security Design for Trust Logic Locking


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SARLock: SAT attack resistant logic locking M Yasin, B Mazumdar, JJV Rajendran, O Sinanoglu 2016 IEEE International Symposium on Hardware Oriented Security and Trust …, 2016	432	2016
On Improving the Security of Logic Locking M Yasin, J Rajendran, O Sinanoglu, R Karri IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015	366	2015
Provably-Secure Logic Locking: From Theory To Practice M Yasin, A Sengupta, M Nabeel, M Ashraf, JJV Rajendran, O Sinanoglu ACM SIGSAC Conference on Computer and Communications Security, 1601-1618, 2017	349	2017
Removal Attacks on Logic Locking and Camouflaging Techniques M Yasin, B Mazumdar, O Sinanoglu, J Rajendran IEEE Transactions on Emerging Topics in Computing, 2017	254	2017
Security Analysis of Anti-SAT M Yasin, B Mazumdar, O Sinanoglu, J Rajendran	182	2016
What to Lock?: Functional and Parametric Locking M Yasin, A Sengupta, BC Schafer, Y Makris, O Sinanoglu, JJV Rajendran Proceedings of the on Great Lakes Symposium on VLSI 2017, 351-356, 2017	131	2017
CamoPerturb: secure IC camouflaging for minterm protection M Yasin, B Mazumdar, O Sinanoglu, J Rajendran Proceedings of the 35th International Conference on Computer-Aided Design, 29, 2016	112	2016
Keynote: A Disquisition on Logic Locking A Chakraborty, NG Jayasankaran, Y Liu, J Rajendran, O Sinanoglu, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019	99	2019
ATPG-based cost-effective, secure logic locking A Sengupta, M Nabeel, M Yasin, O Sinanoglu 2018 IEEE 36th VLSI Test Symposium (VTS), 1-6, 2018	85	2018
Evolution of logic locking M Yasin, O Sinanoglu 2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017	72	2017
Activation of logic encrypted chips: Pre-test or post-test? M Yasin, SM Saeed, J Rajendran, O Sinanoglu 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 139-144, 2016	72	2016
Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases M Yasin, T Tekeste, H Saleh, B Mohammad, O Sinanoglu, M Ismail IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2624-2637, 2017	71	2017
Security analysis of logic encryption against the most effective side-channel attack: DPA M Yasin, B Mazumdar, SS Ali, O Sinanoglu 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2015	60	2015
Transforming between logic locking and IC camouflaging M Yasin, O Sinanoglu 2015 10th International Design & Test Symposium (IDT), 1-4, 2015	47	2015
ScanSAT: unlocking obfuscated scan chains L Alrahis, M Yasin, H Saleh, B Mohammad, M Al-Qutayri, O Sinanoglu Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019	45	2019
Trustworthy Hardware Design: Combinational Logic Locking Techniques M Yasin, Jeyavijayan (JV). Rajendran, O Sinanoglu Springer, 2020	38	2020
ScanSAT: Unlocking static and dynamic scan obfuscation L Alrahis, M Yasin, N Limaye, H Saleh, B Mohammad, M Al-Qutayri, ... IEEE Transactions on Emerging Topics in Computing 9 (4), 1867-1882, 2019	38	2019
MixLock: Securing mixed-signal circuits via logic locking J Leonhard, M Yasin, S Turk, M Nabeel, MM Louërat, R Chotin-Avot, ... Design, Automation and Test in Europe (DATE 2019), 84-89, 2019	38	2019
Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging M Yasin, O Sinanoglu, J Rajendran IEEE Transactions on Information Forensics and Security 12 (11), 2668-2682, 2017	37	2017
TTLock: Tenacious and traceless logic locking M Yasin, B Mazumdar, JJV Rajendran, O Sinanoglu 2017 IEEE International Symposium on Hardware Oriented Security and Trust …, 2017	34	2017

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