| The ISPD-2012 discrete cell sizing contest and benchmark suite MM Ozdal, C Amin, A Ayupov, S Burns, G Wilke, C Zhuo Proceedings of the 2012 ACM international symposium on International …, 2012 | 113 | 2012 |
| An improved benchmark suite for the ISPD-2013 discrete cell sizing contest MM Ozdal, C Amin, A Ayupov, SM Burns, GR Wilke, C Zhuo Proceedings of the 2013 ACM International symposium on Physical Design, 168-170, 2013 | 63 | 2013 |
| Clock distribution architectures: A comparative study C Yeh, G Wilke, H Chen, S Reddy, H Nguyen, T Miyoshi, W Walker, ... 7th International Symposium on Quality Electronic Design (ISQED'06), 7 pp.-91, 2006 | 62 | 2006 |
| A sliding window scheme for accurate clock mesh analysis H Chen, C Yeh, G Wilke, S Reddy, H Nguyen, W Walker, R Murgai ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 52 | 2005 |
| Revisiting automated physical synthesis of high-performance clock networks MR Guthaus, G Wilke, R Reis ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (2 …, 2013 | 46 | 2013 |
| Non-uniform clock mesh optimization with linear programming buffer insertion MR Guthaus, G Wilke, R Reis Proceedings of the 47th Design Automation Conference, 74-79, 2010 | 40 | 2010 |
| High-performance clock mesh optimization MR Guthaus, X Hu, G Wilke, G Flach, R Reis ACM Transactions on Design Automation of Electronic Systems (TODAES) 17 (3 …, 2012 | 31 | 2012 |
| Analyzing timing uncertainty in mesh-based clock architectures SM Reddy, GR Wilke, R Murgai Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 20 | 2006 |
| A silicon-validated methodology for power delivery modeling and simulation C Zhuo, G Wilke, R Chakraborty, A Aydiner, S Chakravarty, WK Shih Proceedings of the International Conference on Computer-Aided Design, 255-262, 2012 | 19 | 2012 |
| Gate sizing minimizing delay and area G Posser, G Flach, G Wilke, R Reis 2011 IEEE Computer Society Annual Symposium on VLSI, 315-316, 2011 | 15 | 2011 |
| Design and analysis of" Tree+ Local Meshes" clock architecture GR Wilke, R Murgai 8th International Symposium on Quality Electronic Design (ISQED'07), 165-170, 2007 | 15 | 2007 |
| A transistor sizing method applied to an automatic layout generation tool C Santos, G Wilke, C Lazzari, R Reis, JL Guntzel 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003 …, 2003 | 15 | 2003 |
| Silicon-validated power delivery modeling and analysis on a 32-nm DDR I/O interface C Zhuo, G Wilke, R Chakraborty, AA Aydiner, S Chakravarty, WK Shih IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (9 …, 2014 | 12 | 2014 |
| A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits S Sawicki, G Wilke, M Johann, R Reis 2009 16th IEEE International Conference on Electronics, Circuits and Systems …, 2009 | 11 | 2009 |
| Gate sizing using geometric programming G Posser, G Flach, G Wilke, R Reis Analog Integrated Circuits and Signal Processing 73, 831-840, 2012 | 10 | 2012 |
| A novel scheme to reduce short-circuit power in mesh-based clock architectures G Wilke, R Fonseca, C Mezzomo, R Reis Proceedings of the 21st annual symposium on Integrated circuits and system …, 2008 | 9 | 2008 |
| A study on layout quality of automatic generated cells G Posser, A Ziesemer, D Guimares, G Wilke, R Reis 2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010 | 8 | 2010 |
| Analyzing timing uncertainty in mesh-based architectures SM Reddy, GR Wilke, R Murgai US Patent 7,801,718, 2010 | 8 | 2010 |
| 3d-via driven partitioning for 3d vlsi integrated circuits S Sawicki, G Wilke, M Johann, R Reis CLEI Electronic Journal 13 (3), 2010 | 7 | 2010 |
| A mesh-buffer displacement optimization strategy G Flach, G Wilke, M Johann, R Reis 2010 IEEE Computer Society Annual Symposium on VLSI, 282-287, 2010 | 6 | 2010 |
