Követés
M B Srinivas
M B Srinivas
További nevekMandalika Srinivas Bala
BITS Pilani, Dubai Campus
E-mail megerősítve itt: dubai.bits-pilani.ac.in
Cím
Hivatkozott rá
Hivatkozott rá
Év
Novel architectures for high-speed and low-power 3-2, 4-2 and 5-2 compressors
S Veeramachaneni, KM Krishna, L Avinash, SR Puppala, MB Srinivas
20th International Conference on VLSI Design held jointly with 6th …, 2007
1832007
A novel reversible TSG gate and its application for designing reversible carry look-ahead and other adder architectures
H Thapliyal, MB Srinivas
Asia-Pacific conference on advances in computer systems architecture, 805-817, 2005
1752005
Novel reversible multiplier architecture using reversible TSG gate
H Thapliyal, MB Srinivas
arXiv preprint cs/0605004, 2006
1722006
A beginning in the reversible logic synthesis of sequential circuits
H Thapliyal, MB Srinivas, M Zwolinski
1632005
High Speed Efficient N x N Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematics
H Thapliyal, MB Srinivas
Enformatika Trans 2, 225-228, 2004
1142004
Novel BCD adders and their reversible logic implementation for IEEE 754r format
H Thapliyal, S Kotiyal, MB Srinivas
19th International Conference on VLSI Design held jointly with 5th …, 2006
992006
Agribot—A multipurpose agricultural robot
A Gollakota, MB Srinivas
2011 Annual IEEE India Conference, 1-4, 2011
822011
VLSI implementation of RSA encryption system using ancient Indian Vedic mathematics
H Thapliyal, MB Srinivas
VLSI Circuits and Systems II 5837, 888-892, 2005
792005
Synthesis of ternary logic circuits using 2: 1 multiplexers
C Vudadha, A Surya, S Agrawal, MB Srinivas
IEEE transactions on circuits and systems I: regular papers 65 (12), 4313-4325, 2018
662018
Novel reversibleTSG'gate and its application for designing components of primitive reversible/quantum ALU
H Thapliyal, MB Srinivas
2005 5th International Conference on Information Communications & Signal …, 2005
632005
A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs.
H Thapliyal, MB Srinivas, HR Arabnia
ESA 5, 106-114, 2005
632005
Design and analysis of a novel parallel square and cube architecture based on ancient Indian Vedic mathematics
H Thapliyal, S Kotiyal, MB Srinivas
48th Midwest Symposium on Circuits and Systems, 2005., 1462-1465, 2005
612005
Novel design and reversible logic synthesis of multiplexer based full adder and multipliers
H Thapliyal, MB Srinivas
48th Midwest Symposium on Circuits and Systems, 2005., 1593-1596, 2005
602005
Multifactor aging of HV generator stator insulation including mechanical vibrations
MB Srinivas, TS Ramu
IEEE Transactions on Electrical Insulation 27 (5), 1009-1021, 1992
581992
A new reversible TSG gate and its application for designing efficient adder circuits
H Thapliyal, MB Srinivas
arXiv preprint cs/0603091, 2006
572006
New improved 1-bit full adder cells
S Veeramachaneni, MB Srinivas
2008 Canadian Conference on Electrical and Computer Engineering, 000735-000738, 2008
562008
A web based expert system shell for fault diagnosis and control of power system equipment
MB Jain, A Jain, MB Srinivas
2008 International Conference on Condition Monitoring and Diagnosis, 1310-1313, 2008
552008
A novel web based expert system architecture for on-line and off-line fault diagnosis and control (FDC) of power system equipment
MB Jain, MB Srinivas, A Jain
2008 Joint International Conference on Power System Technology and IEEE …, 2008
522008
An efficient method of elliptic curve encryption using Ancient Indian Vedic Mathematics
H Thapliyal, MB Srinivas
48th Midwest Symposium on Circuits and Systems, 2005., 826-828, 2005
502005
Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture.
H Thapliyal, MB Srinivas, HR Arabnia
AMCS, 72-76, 2005
452005
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