| A novel low power error detection logic for inexact leading zero anticipator in floating point units BNK Reddy, MC Sekhar, S Veeramachaneni, MB Srinivas 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 4 | 2014 |
| A highly-efficient error detection technique for general matrix multiplication using tiled processing on SIMD architecture CS Mummidi, S Bal, BF Goldstein, S Srinivasan, S Kundu 2022 IEEE 40th International Conference on Computer Design (ICCD), 529-536, 2022 | 3 | 2022 |
| Highly Efficient Self-Checking Matrix Multiplication on Tiled AMX Accelerators CS Mummidi, VC Ferreira, S Srinivasan, S Kundu ACM Transactions on Architecture and Code Optimization 21 (2), 1-22, 2024 | 2 | 2024 |
| A novel fault-tolerant architecture for tiled matrix multiplication S Bal, CS Mummidi, VDC Ferreira, S Srinivasan, S Kundu 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 2 | 2023 |
| ACTION: Adaptive Cache Block Migration in Distributed Cache Architectures C Mummidi, S Kundu ACM Transactions on Architecture and Code Optimization, 2022 | 2 | 2022 |
| Embedded mobile farm robot for identification of diseased plants SS Sadistap, BA Botre, H Pandit, A Rao Fifth International Conference on Digital Image Processing (ICDIP 2013) 8878 …, 2013 | 2 | 2013 |
| Resurrection Attack: Defeating Xilinx MPU's Memory Protection B Madabhushi, CS Mummidi, S Kundu, D Holcomb arXiv preprint arXiv:2405.13933, 2024 | | 2024 |
| A Neural Network-Based Approach to Dynamic Core Morphing for AMPs CS Mummidi, S Kundu 2023 IEEE International Symposium on Smart Electronic Systems (iSES), 4-9, 2023 | | 2023 |
| iSES 2023 CS Mummidi, S Kundu, R Kumar, V Sahula, J Amendola, ... | | |
Sandip KunduUniversity of MassachusettsE-mail megerősítve itt: ecs.umass.edu
