| A memory yield improvement scheme combining built-in self-repair and error correction codes TH Wu, PY Chen, M Lee, BY Lin, CW Wu, CH Tien, HC Lin, H Chen, ... 2012 IEEE International Test Conference, 1-9, 2012 | 36 | 2012 |
| Test cost reduction methodology for InFO wafer-level chip-scale package KL Wang, BY Lin, CW Wu, M Lee, H Chen, HC Lin, CN Peng, MJ Wang IEEE Design & Test 34 (3), 50-58, 2016 | 15 | 2016 |
| On improving interconnect defect diagnosis resolution and yield for interposer-based 3-D ICs CC Chi, BY Lin, CW Wu, MJ Wang, HC Lin, CN Peng IEEE Design & Test 31 (4), 16-26, 2014 | 9 | 2014 |
| A memory failure pattern analyzer for memory diagnosis and repair BY Lin, M Lee, CW Wu 2012 IEEE 30th VLSI Test Symposium (VTS), 234-239, 2012 | 9 | 2012 |
| Symbiotic system models for efficient IOT system design and test CW Wu, BY Lin, HW Hung, SM Tseng, C Chen Test Conference in Asia (ITC-Asia), 2017 International, 71-76, 2017 | 7 | 2017 |
| Redundancy architectures for channel-based 3D DRAM yield improvement BY Lin, WT Chiang, CW Wu, M Lee, HC Lin, CN Peng, MJ Wang 2014 International Test Conference, 1-7, 2014 | 7 | 2014 |
| Exploration methodology for 3D memory redundancy architectures under redundancy constraints BY Lin, M Lee, CW Wu 2013 22nd Asian Test Symposium, 1-6, 2013 | 7 | 2013 |
| Highly reliable and low-cost symbiotic IOT devices and systems BY Lin, HW Hung, SM Tseng, C Chen, CW Wu 2017 IEEE International Test Conference (ITC), 1-10, 2017 | 6 | 2017 |
| A built-off self-repair scheme for channel-based 3D memories HH Liu, BY Lin, CW Wu, WT Chiang, L Mincent, HC Lin, CN Peng, ... IEEE Transactions on Computers 66 (8), 1293-1301, 2017 | 6 | 2017 |
| A local parallel search approach for memory failure pattern identification BY Lin, CW Wu, M Lee, HC Lin, CN Peng, MJ Wang IEEE Transactions on Computers 65 (3), 770-780, 2015 | 5 | 2015 |
| TangleSim: An Agent-based, Modular Simulator for DAG-based Distributed Ledger Technologies BY Lin, D Dziubałtowska, P Macek, A Penzkofer, S Müller 2023 IEEE International Conference on Blockchain and Cryptocurrency (ICBC), 1-5, 2023 | 4 | 2023 |
| Robustness of the tangle 2.0 consensus BY Lin, D Dziubałtowska, P Macek, A Penzkofer, S Müller EAI International Conference on Performance Evaluation Methodologies and …, 2022 | 4 | 2022 |
| System-level test coverage prediction by structural stress test data mining BY Lin, CW Wu, HH Chen VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2015 | 4 | 2015 |
| Efficient probing schemes for fine-pitch pads of info wafer-level chip-scale package YC Huang, BY Lin, CW Wu, M Lee, H Chen, HC Lin, CN Peng, MJ Wang Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 3 | 2016 |
| Controller architecture for low-power, low-latency DRAM with built-in cache ZY Liu, HC Shih, BY Lin, CW Wu IEEE Design & Test 34 (2), 69-78, 2016 | 3 | 2016 |
| Configurable cubical redundancy schemes for channel-based 3-D DRAM yield improvement BY Lin, WT Chiang, CW Wu, M Lee, HC Lin, CN Peng, MJ Wang IEEE Design & Test 33 (2), 30-39, 2015 | 3 | 2015 |
| A fast sweep-line-based failure pattern extractor for memory diagnosis SY Wei, BY Lin, CW Wu 2016 21th IEEE European Test Symposium (ETS), 1-6, 2016 | 2 | 2016 |
| 提升記憶體錯誤辨別率與良率之記憶體測試資料分析方法 BY Lin 清華大學電機工程學系所學位論文 2015, 1-116, 2015 | | 2015 |
Cheng-Wen Wu 吳誠文Department of Electrical Engineering, National Tsing Hua UniversityE-mail megerősítve itt: ee.nthu.edu.tw
