| Effective Method for Simultaneous Gate Sizing and th Assignment Using Lagrangian Relaxation G Flach, T Reimann, G Posser, M Johann, R Reis IEEE transactions on computer-aided design of integrated circuits and …, 2014 | 60 | 2014 |
| Rsyn: An extensible physical synthesis framework G Flach, M Fogaça, J Monteiro, M Johann, R Reis Proceedings of the 2017 ACM on International Symposium on Physical Design, 33-40, 2017 | 33 | 2017 |
| High-performance clock mesh optimization MR Guthaus, X Hu, G Wilke, G Flach, R Reis ACM Transactions on Design Automation of Electronic Systems (TODAES) 17 (3 …, 2012 | 31 | 2012 |
| Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing R Hentschke, G Flach, F Pinto, R Reis Proceedings of the 19th annual symposium on Integrated circuits and systems …, 2006 | 31 | 2006 |
| 3D-vias aware quadratic placement for 3D VLSI circuits R Hentschke, G Flach, F Pinto, R Reis IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07), 67-72, 2007 | 29 | 2007 |
| Drive strength aware cell movement techniques for timing driven placement G Flach, M Fogaça, J Monteiro, M Johann, R Reis Proceedings of the 2016 on International Symposium on Physical Design, 73-80, 2016 | 28 | 2016 |
| Jezz: An effective legalization algorithm for minimum displacement JC Puget, G Flach, M Johann, R Reis Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 1-5, 2015 | 27 | 2015 |
| Simultaneous gate sizing and vt assignment using fanin/fanout ratio and simulated annealing T Reimann, G Posser, G Flach, M Johann, R Reis 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2549-2552, 2013 | 24 | 2013 |
| Gate sizing minimizing delay and area G Posser, G Flach, G Wilke, R Reis 2011 IEEE Computer Society Annual Symposium on VLSI, 315-316, 2011 | 15 | 2011 |
| Quadratic timing objectives for incremental timing-driven placement optimization M Fogaça, G Flach, J Monteiro, M Johann, R Reis 2016 IEEE International Conference on Electronics, Circuits and Systems …, 2016 | 10 | 2016 |
| Simultaneous gate sizing and Vthassignment using Lagrangian Relaxation and delay sensitivities G Flach, T Reimann, G Posser, M Johann, R Reis 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 84-89, 2013 | 10 | 2013 |
| Gate sizing using geometric programming G Posser, G Flach, G Wilke, R Reis Analog Integrated Circuits and Signal Processing 73, 831-840, 2012 | 10 | 2012 |
| Leakage current analysis in static cmos logic gates for a transistor network design approach J Tonfat, G Flach, R Reis 2016 26th International Workshop on Power and Timing Modeling, Optimization …, 2016 | 9 | 2016 |
| Building a bitcoin miner on an FPGA S Oliveira, F Soares, G Flach, M Johann, R Reis South Symposium on Microelectronics 15, 2012 | 9 | 2012 |
| Cell placement on graphics processing units G Flach, M Johann, R Hentschke, R Reis Proceedings of the 20th annual conference on Integrated circuits and systems …, 2007 | 9 | 2007 |
| An incremental timing-driven flow using quadratic formulation for detailed placement G Flach, J Monteiro, M Fogaça, J Puget, P Butzen, M Johann, R Reis 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 6 | 2015 |
| A mesh-buffer displacement optimization strategy G Flach, G Wilke, M Johann, R Reis 2010 IEEE Computer Society Annual Symposium on VLSI, 282-287, 2010 | 6 | 2010 |
| Routing-aware incremental timing-driven placement J Monteiro, NK Darav, G Flach, M Fogaça, R Reis, A Kennings, M Johann, ... 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 290-295, 2016 | 4 | 2016 |
| A tool to simulate optical lithography in nanoCMOS TM Ferla, G Flach, R Reis 2014 IEEE International Instrumentation and Measurement Technology …, 2014 | 4 | 2014 |
| Transistor sizing and gate sizing using geometric programming considering delay minimization G Posser, G Flach, G Wilke, R Reis 10th IEEE International NEWCAS Conference, 85-88, 2012 | 4 | 2012 |
Ricardo Augusto da Luz ReisUFRGSVerified email at inf.ufrgs.br
