| Optimizing FPGA-based accelerator design for deep convolutional neural networks C Zhang, P Li, G Sun, Y Guan, B Xiao, J Cong Proceedings of the 2015 ACM/SIGDA international symposium on field …, 2015 | 2495 | 2015 |
| High-Level Synthesis for FPGAs: From Prototyping to Deployment Cong | 1046* | |
| FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs J Cong, Y Ding IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994 | 847 | 1994 |
| Caffeine: Toward uniformed representation and acceleration for deep convolutional neural networks C Zhang, G Sun, Z Fang, P Zhou, P Pan, J Cong IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 705 | 2018 |
| A thermal-driven floorplanning algorithm for 3D ICs J Cong, J Wei, Y Zhang IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 561 | 2004 |
| Minimizing computation in convolutional neural networks J Cong, B Xiao International conference on artificial neural networks, 281-290, 2014 | 482 | 2014 |
| Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs X Wei, CH Yu, P Zhang, Y Chen, Y Wang, H Hu, Y Liang, J Cong Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 477 | 2017 |
| Scaling for edge inference of deep neural networks X Xu, Y Ding, SX Hu, M Niemier, J Cong, Y Hu, Y Shi Nature Electronics 1 (4), 216-222, 2018 | 424 | 2018 |
| Performance optimization of VLSI interconnect layout J Cong, L He, CK Koh, PH Madden Integration 21 (1-2), 1-94, 1996 | 411 | 1996 |
| FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates Y Guan, H Liang, N Xu, W Wang, S Shi, X Chen, G Sun, W Zhang, J Cong 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017 | 399 | 2017 |
| CMP network-on-chip overlaid with multi-band RF-interconnect MF Chang, J Cong, A Kaplan, M Naik, G Reinman, E Socher, SW Tam 2008 IEEE 14th International Symposium on High Performance Computer …, 2008 | 365 | 2008 |
| Application-specific instruction generation for configurable processor architectures J Cong, Y Fan, G Han, Z Zhang Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field …, 2004 | 306 | 2004 |
| Combinational logic synthesis for LUT based field programmable gate arrays J Cong, Y Ding ACM Transactions on Design Automation of Electronic Systems (TODAES) 1 (2 …, 1996 | 290 | 1996 |
| On area/depth trade-off in LUT-based FPGA technology mapping J Cong, Y Ding Proceedings of the 30th International Design Automation Conference, 213-218, 1993 | 286 | 1993 |
| Provably good performance-driven global routing J Cong, AB Kahng, G Robins, M Sarrafzadeh, CK Wong IEEE transactions on computer-aided design of integrated circuits and …, 1992 | 284 | 1992 |
| SACNN: Self-attention convolutional neural network for low-dose CT denoising with self-supervised perceptual loss network M Li, W Hsu, X Xie, J Cong, W Gao IEEE transactions on medical imaging 39 (7), 2289-2301, 2020 | 279 | 2020 |
| An interconnect-centric design flow for nanometer technologies J Cong Proceedings of the IEEE 89 (4), 505-528, 2001 | 279 | 2001 |
| Energy-efficient CNN implementation on a deeply pipelined FPGA cluster C Zhang, D Wu, J Sun, G Sun, G Luo, J Cong Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | 271 | 2016 |
| A scalable micro wireless interconnect structure for CMPs SB Lee, SW Tam, I Pefkianakis, S Lu, MF Chang, C Guo, G Reinman, ... Proceedings of the 15th annual international conference on Mobile computing …, 2009 | 271 | 2009 |
| mPL6: Enhanced multilevel mixed-size placement TF Chan, J Cong, JR Shinnerl, K Sze, M Xie Proceedings of the 2006 international symposium on Physical design, 212-214, 2006 | 268* | 2006 |
Glenn ReinmanProfessor of Computer Science, UCLAVerified email at cs.ucla.edu
