| Using run-time reconfiguration for fault injection in hardware prototypes L Antoni, R Leveugle, M Feher 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2002 | 181 | 2002 |
| Using run-time reconfiguration for fault injection applications L Antoni, R Leveugle, B Fehér IEEE Transactions on Instrumentation and Measurement 52 (5), 1468-1473, 2003 | 131 | 2003 |
| A full-parallel digital implementation for pre-trained NNs T Szabó, L Antoni, G Horváth, B Fehér Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural …, 2000 | 38 | 2000 |
| Acoustic source localization fusing sparse direction of arrival estimates A Ledeczi, G Kiss, B Feher, P Volgyesi, G Balogh 2006 International Workshop on Intelligent Solutions in Embedded Systems, 1-13, 2006 | 30 | 2006 |
| Molecular docking on FPGA and GPU platforms I Pechan, B Feher 2011 21st International Conference on Field Programmable Logic and …, 2011 | 26 | 2011 |
| Application of partial reconfiguration of FPGAs in image processing T Raikovich, B Fehér 6th Conference on Ph. D. Research in Microelectronics & Electronics, 1-4, 2010 | 21 | 2010 |
| FPGA-based acceleration of the AutoDock molecular docking software I Pechan, B Fehér, A Bérces 6th Conference on Ph. D. Research in Microelectronics & Electronics, 1-4, 2010 | 18 | 2010 |
| Efficient synthesis of distributed vector multipliers B Fehér Microprocessing and microprogramming 38 (1-5), 345-350, 1993 | 17 | 1993 |
| Dependability analysis: A new application for run-time reconfiguration R Leveugle, L Antoni, B Fehér Proceedings International Parallel and Distributed Processing Symposium, 7 pp., 2003 | 15 | 2003 |
| Digital filters based on recursive Walsh-Hadamard transformation G Peceli, B Feher IEEE transactions on circuits and systems 37 (1), 150-152, 1990 | 15 | 1990 |
| Acoustic source localization with high performance sensor nodes MR Azimi-Sadjadi, G Kiss, B Fehér, S Srinivasan, A Ledeczi Unattended Ground, Sea, and Air Sensor Technologies and Applications IX 6562 …, 2007 | 14 | 2007 |
| Hardware accelerated molecular docking: A survey I Pechan, B Fehér Bioinformatics 133, 142-165, 2012 | 13 | 2012 |
| Neural network implementation using distributed arithmetic T Szabó, B Fehér, G Horváth 1998 Second International Conference. Knowledge-Based Intelligent Electronic …, 1998 | 12 | 1998 |
| Hierarchical histogram-based median filter for gpus P Szántó, B Fehér Acta Polytechnica Hungarica 15 (2), 49-68, 2018 | 11 | 2018 |
| Efficient implementation of convolutional neural networks on FPGA A Hadnagy, B Fehér, T Kovácsházy 2018 19th International Carpathian Control Conference (ICCC), 359-364, 2018 | 8 | 2018 |
| An efficient implementation for a matrix-vector multiplier structure T Szabó, L Antoni, G Horváth, B Fehér Proceedings of IEEE International Joint Conference on Neural Networtks …, 2000 | 6 | 2000 |
| Scalable architecture for rank order filtering P Szántó, G Szedo, B Fehér, WC Chung US Patent 8,005,881, 2011 | 5 | 2011 |
| Parallel sorting algorithms in fpga A Széll 13Th Phd Mini-Symposium, 8, 2006 | 5 | 2006 |
| Application of bit-serial arithmetic units for FPGA implementation of convolutional neural networks G Csordás, B Fehér, T Kovácsházy 2018 19th International Carpathian Control Conference (ICCC), 322-327, 2018 | 4 | 2018 |
| High‐Performance Timing‐Driven Rank Filter P Szántó, G Szedő, B Fehér VLSI Design 2008 (1), 753043, 2008 | 4 | 2008 |
| Resonator based digital filters using field programmable gate array elements B Fehér [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and …, 1992 | 4 | 1992 |
| Scalable architecture for rank order filtering P Szanto, G Szedo, B Feher, WC Chung US Patent 8,713,082, 2014 | 3 | 2014 |
| Implementing 2D median filter in FPGAs P Szántó, G Szedő, B Fehér Proceedings of the 7th International Carpathian Control Conference (ICCC’06), 2006 | 3 | 2006 |
| New inner product algorithm of the two-dimensional DCT B Feher Digital Video Compression: Algorithms and Technologies 1995 2419, 436-444, 1995 | 3 | 1995 |
| Coefficient-dependent logic synthesis of FIR digital filters B Feher Microelectronics journal 25 (3), 229-235, 1994 | 3 | 1994 |
| FPGA-based BLAST prefiltering P Laczkó, B Fehér, B Benyó 2010 IEEE 14th International Conference on Intelligent Engineering Systems …, 2010 | 2 | 2010 |
| Implementing a Global Optimization Algorithm Related To Bioinformatics with a High-Performance FPGA I Pechan Proceedings of the Sixteenth PhD Mini-Symposium, Budapest University of …, 2009 | 2 | 2009 |
| Efficient sorting architectures in FPGA A Széll, B Fehér Proc. Int. Carpathian Control Conf.(ICCC), 1-4, 2006 | 2 | 2006 |
| High performance visibility testing with screen segmentation P Szántó, B Fehér 2nd Workshop onEmbedded Systems for Real-Time Multimedia, 2004. ESTImedia …, 2004 | 2 | 2004 |
| Image Processing using Reconfigurable hardware T Raikovich Proc. of the 16th PhD Mini-Symposium, 40-43, 0 | 2 | |
| Accelerating virtual screening of compound libraries P Szántó, B Fehér, A Bérces Many-Core and Reconfigurable Supercomputing Conference (MRSC 09), 2009 | 1 | 2009 |
| LOGSYS Development Environment B Fehér, T Raikovich, P Laczkó Proc. of EWME, Budapest, 94-95, 2008 | 1 | 2008 |
| LOGSYS–Development Environment of Embedded Systems T Raikovich, B Fehér, P Laczkó Proceedings of RCEAS, 2007 | 1 | 2007 |
| Exact Bucket Sorting for Segmented Screen Rendering P Szántó, B Fehér GSPX, 2005 | 1 | 2005 |
| Cost effective 2x2 inner product processors B Fehér, G Szedö Lecture notes in computer science, 348-355, 1998 | 1 | 1998 |
| Program slicing based on runtime dataflow measurements G Wacha, J Lazányi, B Fehér Proceedings of the 2015 16th International Carpathian Control Conference …, 2015 | | 2015 |
| EXAMINATION OF ALGORITHMS USING DYNAMIC DATA FLOW GRAPHS G WACHA 21ST PHD MINI-SYMPOSIUM, 44, 2014 | | 2014 |
| Reconfigurable Image Processing Pipeline T Raikovich | | 2010 |
| LOGSYS: A simple tool for complex student projects B Fehér, T Raikovich, G Dancsi, P Laczkó 2009 IEEE International Conference on Microelectronic Systems Education, 33-36, 2009 | | 2009 |
| Antialiasing IN Segmented Rendering P SZÁNTÓ 13TH PHD MINI-SYMPOSIUM, 10, 2006 | | 2006 |
| Memory Profiling Based Hardware–Software Co-DESIGN IN FPGA J LAZÁNYI 13TH PHD MINI-SYMPOSIUM, 12, 2006 | | 2006 |
| Distributed embedded system using single FPGA J Lazányi, B Fehér Vysoká škola báňská-Technická univerzita Ostrava, 2006 | | 2006 |
| 3D rendering using FPGAs. P Szántó, B Fehér VLSI-SOC, 149-154, 2003 | | 2003 |
| Published in the Proceedings of The Nineteenth Euromicro Conference, Barcelona, 6-9. Sept. 1993. Microprocessing and Microprogramming, Vol. 38. pp. 345-350. Efficient Synthesis … B Fehér Microprocessing and Microprogramming 38, 345-350, 1993 | | 1993 |
| Hungarian Patents B Fehér Mérés és Automatika 34 (8), 323-325, 1986 | | 1986 |
| Analysis of indoor active acoustic source tracking G Kiss, M Azimi, B Fehér REGIONAL CONFERENCE ON EMBEDDED AND AMBIENT SYSTEMS, 28, 0 | | |
| High Speed FPGA Implementation of Median Filters B Fehér, G Szedő | | |
| Accelerating SOLiD short read assembly with GPU P Szántó, B Fehér, A Széll | | |
| Dependability Analysis: A New Application for Run-Time Reconfiguration. B Fehér | | |
| Újrakonfigurálható technológiák nagyteljesítményű alkalmazásai VIMIM364 3. szemeszter 2/1/0/v 4 kredit Előadás: H12. 15-14.00 IE321 Gyakorlat: PáratlanPéntek 10.15-12.00 IE321 … A Fehér, B Fehér | | |
| Szabadalmak G Péceli, B Fehér, F Nagy | | |
| LOGSYS–Development Environment of Embedded Systems B Fehér, T Raikovich, P Laczkó REGIONAL CONFERENCE ON EMBEDDED AND AMBIENT SYSTEMS, 74, 0 | | |
| Gábor Szedo FPGA Based Reconfigurable Logics Minisymposium, Techical University of Budapest Department of Measurement and Instrumentation, February 1997, Proceedings, pp. 38-39 … G Szedo, B Fehér | | |
| NoNLINEAR FilterS on Reconfigurable PROCESSORS B Fehér, G Szedő | | |
| Our current Projects B Feher, G Horvath, T Szabo, T Kovacshazy, G Szedo, L Antoni | | |
| Implementing a Programmable Pixel Pipeline in FPGAs P Szántó, B Fehér | | |
| Hardware Implementation of a Programmable Pixel Pipeline P Szántó, B Fehér | | |
| Scalable Rasterizer Unit P Szántó, B Fehér | | |
| Sborník vědeckých prací Vysoké školy báňské-Technické univerzity Ostrava C SZABÓ, M IMECS, II INCZE | | |
| Author’s Index A Ademaj, F Afonso, M Albero, M Bader, G Balogh, G Benet, F Blanes, ... | | |
| Efficient and Scalable 3D Rendering Architecture P Szántó, B Fehér | | |
| EFFICIENT MULTI-CHANNEL FIR FILTERS IN FPGA P SZÁNTÓ, J LAZÁNYI, B FEHÉR | | |
