Béla Fehér
TitleCited byYear
Using run-time reconfiguration for fault injection in hardware prototypes
L Antoni, R Leveugle, M Feher
17th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2002
1532002
Using run-time reconfiguration for fault injection applications
L Antoni, R Leveugle, B Fehér
IEEE Transactions on Instrumentation and Measurement 52 (5), 1468-1473, 2003
1152003
A full-parallel digital implementation for pre-trained NNs
T Szabó, L Antoni, G Horváth, B Fehér
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural …, 2000
302000
Acoustic source localization fusing sparse direction of arrival estimates
A Ledeczi, G Kiss, B Feher, P Volgyesi, G Balogh
2006 International Workshop on Intelligent Solutions in Embedded Systems, 1-13, 2006
232006
Efficient synthesis of distributed vector multipliers
B Fehér
Microprocessing and microprogramming 38 (1-5), 345-350, 1993
181993
Application of partial reconfiguration of FPGAs in image processing
T Raikovich, B Fehér
6th Conference on Ph. D. Research in Microelectronics & Electronics, 1-4, 2010
142010
Digital filters based on recursive Walsh-Hadamard transformation
G Peceli, B Feher
IEEE transactions on circuits and systems 37 (1), 150-152, 1990
141990
Molecular docking on FPGA and GPU platforms
I Pechan, B Feher
2011 21st International Conference on Field Programmable Logic and …, 2011
132011
Acoustic source localization with high performance sensor nodes
MR Azimi-Sadjadi, G Kiss, B Fehér, S Srinivasan, A Ledeczi
Unattended Ground, Sea, and Air Sensor Technologies and Applications IX 6562 …, 2007
132007
Dependability analysis: A new application for run-time reconfiguration
R Leveugle, L Antoni, B Fehér
Proceedings International Parallel and Distributed Processing Symposium, 7 pp., 2003
132003
FPGA-based acceleration of the AutoDock molecular docking software
I Pechan, B Fehér, A Bérces
6th Conference on Ph. D. Research in Microelectronics & Electronics, 1-4, 2010
92010
Neural network implementation using distributed arithmetic
T Szabó, B Fehér, G Horváth
1998 Second International Conference. Knowledge-Based Intelligent Electronic …, 1998
91998
Hardware accelerated molecular docking: A survey
I Pechan, B Feher
Bioinformatics, 133, 2012
62012
An efficient implementation for a matrix-vector multiplier structure
T Szabó, L Antoni, G Horváth, B Fehér
Proceedings of IEEE International Joint Conference on Neural Networtks …, 2000
62000
Coefficient-dependent logic synthesis of FIR digital filters
B Feher
Microelectronics journal 25 (3), 229-235, 1994
51994
Resonator based digital filters using field programmable gate array elements
B Fehér
[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and …, 1992
41992
Scalable architecture for rank order filtering
P Szántó, G Szedo, B Fehér, WC Chung
US Patent 8,005,881, 2011
32011
High Performance Timing-Driven Rank Filter
P Szántó, B Fehér, G Szedo
2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006
32006
FPGA-based BLAST prefiltering
P Laczkó, B Fehér, B Benyó
2010 IEEE 14th International Conference on Intelligent Engineering Systems …, 2010
22010
Efficient sorting architectures in FPGA
A Széll, B Fehér
Proc. Int. Carpathian Control Conf.(ICCC), 1-4, 2006
22006
High performance visibility testing with screen segmentation
P Szántó, B Fehér
2nd Workshop onEmbedded Systems for Real-Time Multimedia, 2004. ESTImedia …, 2004
22004
Efficient implementation of convolutional neural networks on FPGA
A Hadnagy, B Fehér, T Kovácsházy
2018 19th International Carpathian Control Conference (ICCC), 359-364, 2018
12018
Hierarchical Histogram-based Median Filter for GPUs
P Szántó, B Fehér
Acta Polytechnica Hungarica 15 (2), 2018
12018
Scalable architecture for rank order filtering
P Szanto, G Szedo, B Feher, WC Chung
US Patent 8,713,082, 2014
12014
Accelerating virtual screening of compound libraries
P Szántó, B Fehér, A Bérces
Many-Core and Reconfigurable Supercomputing Conference (MRSC 09), 2009
12009
LOGSYS Development Environment
B Fehér, T Raikovich, P Laczkó
Proc. of EWME, Budapest, 94-95, 2008
12008
LOGSYS–Development Environment of Embedded Systems
T Raikovich, B Fehér, P Laczkó
Proceedings of RCEAS, 2007
12007
Scalable Rasterizer Unit
P Szántó, B Fehér
Budapest University of Technology Department of Measurement and Information …, 2006
12006
Implementing 2D median filter in FPGAs
P Szántó, G Szedő, B Fehér
Vysoká škola báňská-Technická univerzita Ostrava, 2006
12006
Exact Bucket Sorting for Segmented Screen Rendering
P Szántó, B Fehér
GSPX, 2005
12005
Cost effective 2× 2 inner product processors
B Fehér, G SzedŐ
International Workshop on Field Programmable Logic and Applications, 348-355, 1998
11998
Application of bit-serial arithmetic units for FPGA implementation of convolutional neural networks
G Csordás, B Fehér, T Kovácsházy
2018 19th International Carpathian Control Conference (ICCC), 322-327, 2018
2018
Program slicing based on runtime dataflow measurements
G Wacha, J Lazányi, B Fehér
Proceedings of the 2015 16th International Carpathian Control Conference …, 2015
2015
FPGA implementation of cheminformatics and computational chemistry algorithms and its cost/performance comparison with GPGPU, cloud computing and SIMD implementations
A Berces, B Feher, P Szanto, I Pechan, L Lajko, Z Runyo, P Laczko, ...
ABSTRACTS OF PAPERS OF THE AMERICAN CHEMICAL SOCIETY 240, 2010
2010
LOGSYS: A simple tool for complex student projects
B Fehér, T Raikovich, G Dancsi, P Laczkó
2009 IEEE International Conference on Microelectronic Systems Education, 33-36, 2009
2009
Distributed embedded system using single FPGA
J Lazányi, B Fehér
Vysoká škola báňská-Technická univerzita Ostrava, 2006
2006
3D rendering using FPGAs.
P Szántó, B Fehér
VLSI-SOC, 149-154, 2003
2003
New inner product algorithm of the two-dimensional DCT
B Feher
Digital Video Compression: Algorithms and Technologies 1995 2419, 436-444, 1995
1995
Published in the Proceedings of The Nineteenth Euromicro Conference, Barcelona, 6-9. Sept. 1993. Microprocessing and Microprogramming, Vol. 38. pp. 345-350. Efficient Synthesis …
B Fehér
Microprocessing and Microprogramming 38, 345-350, 1993
1993
Hungarian Patents
B Fehér
Mérés és Automatika 34 (8), 323-325, 1986
1986
High Speed FPGA Implementation of Median Filters
B Fehér, G Szedő
Accelerating SOLiD short read assembly with GPU
P Szántó, B Fehér, A Széll
Dependability Analysis: A New Application for Run-Time Reconfiguration.
B Fehér
Újrakonfigurálható technológiák nagyteljesítményű alkalmazásai VIMIM364 3. szemeszter 2/1/0/v 4 kredit Előadás: H12. 15-14.00 IE321 Gyakorlat: PáratlanPéntek 10.15-12.00 IE321 …
A Fehér, B Fehér
Szabadalmak
G Péceli, B Fehér, F Nagy
LOGSYS–Development Environment of Embedded Systems
B Fehér, T Raikovich, P Laczkó
Gábor Szedo FPGA Based Reconfigurable Logics Minisymposium, Techical University of Budapest Department of Measurement and Instrumentation, February 1997, Proceedings, pp. 38-39 …
G Szedo, B Fehér
NoNLINEAR FilterS on Reconfigurable PROCESSORS
B Fehér, G Szedő
Our current Projects
B Feher, G Horvath, T Szabo, T Kovacshazy, G Szedo, L Antoni
Implementing a Programmable Pixel Pipeline in FPGAs
P Szántó, B Fehér
Hardware Implementation of a Programmable Pixel Pipeline
P Szántó, B Fehér
Sborník vědeckých prací Vysoké školy báňské-Technické univerzity Ostrava
P SZÁNTÓ, G SZEDŐ, B FEHÉR
Author’s Index
A Ademaj, F Afonso, M Albero, M Bader, G Balogh, G Benet, F Blanes, ...
Efficient and Scalable 3D Rendering Architecture
P Szántó, B Fehér
EFFICIENT MULTI-CHANNEL FIR FILTERS IN FPGA
P SZÁNTÓ, J LAZÁNYI, B FEHÉR
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