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Sanjay Prajapati
Sanjay Prajapati
Verified email at iitr.ac.in
Title
Cited by
Cited by
Year
Organic thin-film transistor applications: Materials to circuits
BK Kaushik, B Kumar, S Prajapati, P Mittal
CRC Press, 2016
372016
Next generation spin torque memories
BK Kaushik, S Verma, AA Kulkarni, S Prajapati
Springer, 2017
242017
Area and energy efficient series multilevel cell STT-MRAMs for optimized read–write operations
S Prajapati, BK Kaushik
IEEE Transactions on Magnetics 55 (1), 1-10, 2018
152018
Modeling of a magnetic tunnel junction for a multilevel STT-MRAM cell
S Prajapati, S Verma, AA Kulkarni, BK Kaushik
IEEE Transactions on Nanotechnology 18, 1005-1014, 2018
142018
Energy-efficient differential spin Hall MRAM-based 4-2 magnetic compressor
V Nehra, S Prajapati, P Tankwal, Z Zilic, TN Kumar, BK Kaushik
IEEE Transactions on Magnetics 56 (1), 1-11, 2019
112019
High-performance computing-in-memory architecture using STT-/SOT-based series triple-level cell MRAM
V Nehra, S Prajapati, TN Kumar, BK Kaushik
IEEE Transactions on Magnetics 57 (8), 1-12, 2021
102021
Parallel multilevel cell STT-MRAMs for optimized area energy and read–write operations
S Prajapati, BK Kaushik
IEEE Transactions on Magnetics 54 (6), 1-9, 2018
102018
Optimal Boolean Logic Quantum Circuit Decomposition for Spin-Torque-Based -Qubit Architecture
A Kulkarni, S Prajapati, S Verma, BK Kaushik
IEEE Transactions on Magnetics 54 (10), 1-9, 2018
62018
Area and energy efficient magnetic full adder based on differential spin hall MRAM
S Prajapati, Z Zilic, BK Kaushik
2018 16th IEEE International New Circuits and Systems Conference (NEWCAS …, 2018
62018
Transmission Coefficient Matrix Modeling of Spin-Torque-Based-Qubit Architecture
A Kulkarni, S Prajapati, BK Kaushik
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (8 …, 2018
62018
High-performance computing-in-memory architecture based on single-level and multilevel cell differential spin Hall MRAM
S Prajapati, V Nehra, BK Kaushik
IEEE Transactions on Magnetics 57 (9), 1-15, 2021
52021
Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates
P Tankwal, V Nehra, S Prajapati, BK Kaushik
Circuit world 45 (4), 300-310, 2019
42019
Next generation 3-D spin transfer torque magneto-resistive random access memories
BK Kaushik, S Verma, AA Kulkarni, S Prajapati, BK Kaushik, S Verma, ...
Next Generation Spin Torque Memories, 13-34, 2017
22017
Novel compact model for multi-level spin torque magnetic tunnel junctions
S Prajapati, S Verma, AA Kulkarni, BK Kaushik
Spintronics IX 9931, 84-92, 2016
22016
Low Energy and Write-Efficient Spin-Orbit Torque based Triple-Level Cell MRAM
S Dhull, A Nisar, V Nehra, S Prajapati, TN Kumar, BK Kaushik
IEEE Transactions on Magnetics, 2023
12023
Magnetic Domain Wall Race Track Memory
BK Kaushik, S Verma, AA Kulkarni, S Prajapati, BK Kaushik, S Verma, ...
Next Generation Spin Torque Memories, 71-92, 2017
12017
Particle Swarm Optimization with Memory Loss Operation
RA Thakker, SB Prajapati, MB Patil
Department of Electrical Engineering, Indian Institute of Technology Bombay …, 2009
12009
Differential spin Hall MRAM based low power logic circuits and multipliers
V Nehra, S Prajapati, TN Kumar, BK Kaushik
Semiconductor Science and Technology 37 (7), 075007, 2022
2022
Next generation 3-D spin transfer torque magneto-resistive random access memories
B Kumar Kaushik, S Verma, AA Kulkarni, S Prajapati
SpringerBriefs in Applied Sciences and Technology, 2017
2017
Magnetic domain wall race track memory
B Kumar Kaushik, S Verma, AA Kulkarni, S Prajapati
SpringerBriefs in Applied Sciences and Technology, 2017
2017
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Articles 1–20