| HERMES: an infrastructure for low area overhead packet-switching networks on chip F Moraes, N Calazans, A Mello, L Möller, L Ost Integration 38 (1), 69-93, 2004 | 832 | 2004 |
| Accuracy evaluation of gem5 simulator system A Butko, R Garibotti, L Ost, G Sassatelli 7th International workshop on reconfigurable and communication-centric …, 2012 | 221 | 2012 |
| MAIA: a framework for networks on chip generation and verification L Ost, A Mello, J Palma, F Moraes, N Calazans Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 103 | 2005 |
| Evaluation of routing algorithms on mesh based nocs AV de Mello, LC Ost, FG Moraes, NLV Calazans PUCRS, Av. Ipiranga 22, 2004 | 84 | 2004 |
| RTOS scheduler implementation in hardware and software for real time applications M Vetromille, L Ost, CAM Marcon, C Reif, F Hessel Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06 …, 2006 | 76 | 2006 |
| A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. FG Moraes, A Mello, L Möller, L Ost, NLV Calazans VLSI-SOC, 318-323, 2003 | 70 | 2003 |
| A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability F Rosa, F Kastensmidt, R Reis, L Ost 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2015 | 54 | 2015 |
| Energy-aware dynamic task mapping for NoC-based MPSoCs M Mandelli, L Ost, E Carara, G Guindani, T Gouvea, G Medeiros, ... 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 1676-1679, 2011 | 54 | 2011 |
| Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach L Ost, M Mandelli, GM Almeida, L Moller, LS Indrusiak, G Sassatelli, ... ACM Transactions on Embedded Computing Systems (TECS) 12 (3), 1-22, 2013 | 51 | 2013 |
| Using machine learning techniques to evaluate multicore soft error reliability FR da Rosa, R Garibotti, L Ost, R Reis IEEE Transactions on Circuits and Systems I: Regular Papers 66 (6), 2151-2164, 2019 | 49 | 2019 |
| Multi-task dynamic mapping onto NoC-based MPSoCs M Mandelli, A Amory, L Ost, FG Moraes Proceedings of the 24th symposium on Integrated circuits and systems design …, 2011 | 49 | 2011 |
| A trace-driven approach for fast and accurate simulation of manycore architectures A Butko, R Garibotti, L Ost, V Lapotre, A Gamatie, G Sassatelli, ... The 20th Asia and South Pacific Design Automation Conference, 707-712, 2015 | 46 | 2015 |
| Reliability on ARM processors against soft errors through SIHFT techniques E Chielle, F Rosa, GS Rodrigues, LA Tambara, J Tonfat, E Macchione, ... IEEE Transactions on Nuclear Science 63 (4), 2208-2216, 2016 | 40 | 2016 |
| Exploring NoC-based MPSoC design space with power estimation models L Ost, G Guindani, F Moraes, L Indrusiak, S Määttä IEEE Design & Test of Computers 28 (2), 16-29, 2010 | 39* | 2010 |
| Analyzing the impact of fault-tolerance methods in arm processors under soft errors running linux and parallelization apis GS Rodrigues, F Rosa, ÁB de Oliveira, FL Kastensmidt, L Ost, R Reis IEEE Transactions on Nuclear Science 64 (8), 2196-2203, 2017 | 38 | 2017 |
| Open-scale: A scalable, open-source noc-based mpsoc for design space exploration R Busseuil, L Barthe, GM Almeida, L Ost, F Bruguier, G Sassatelli, ... 2011 International Conference on Reconfigurable Computing and FPGAs, 357-362, 2011 | 32 | 2011 |
| Applying lightweight soft error mitigation techniques to embedded mixed precision deep neural networks G Abich, J Gava, R Garibotti, R Reis, L Ost IEEE Transactions on Circuits and Systems I: Regular Papers 68 (11), 4772-4782, 2021 | 30 | 2021 |
| Instruction-driven timing CPU model for efficient embedded software development using OVP F Rosa, L Ost, R Reis, G Sassatelli 2013 IEEE 20th International Conference on Electronics, Circuits, and …, 2013 | 29 | 2013 |
| Fast energy evaluation of embedded applications for many-core systems F Rosa, L Ost, T Raupp, F Moraes, R Reis 2014 24th International Workshop on Power and Timing Modeling, Optimization …, 2014 | 28 | 2014 |
| Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliability M Mandelli, L Ost, G Sassatelli, F Moraes Sixteenth International Symposium on Quality Electronic Design, 392-396, 2015 | 23 | 2015 |
Fernando Gehm MoraesProfessor at the School of Technology at PUCRSVerified email at pucrs.br
