Követés
Aporva Amarnath
Aporva Amarnath
IBM Research
E-mail megerősítve itt: ibm.com
Cím
Hivatkozott rá
Hivatkozott rá
Év
OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator
S Pal, J Beaumont, DH Park, A Amarnath, S Feng, C Chakrabarti, HS Kim, ...
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
2632018
The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips
S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ...
IEEE Micro 38 (2), 30-41, 2018
1232018
Sparse-TPU: Adapting systolic arrays for sparse matrices
X He, S Pal, A Amarnath, S Feng, DH Park, A Rovinski, H Ye, Y Chen, ...
Proceedings of the 34th ACM international conference on supercomputing, 1-12, 2020
792020
Celerity: An open source RISC-V tiered accelerator fabric
T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ...
Symp. on High Performance Chips (Hot Chips), 2017
372017
A 7.3 m output non-zeros/j, 11.7 m output non-zeros/gb reconfigurable sparse matrix–matrix multiplication accelerator
DH Park, S Pal, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ...
IEEE Journal of Solid-State Circuits 55 (4), 933-944, 2020
302020
A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
2019 Symposium on VLSI Circuits, C30-C31, 2019
302019
Evaluating celerity: A 16-nm 695 Giga-RISC-V instructions/s manycore processor with synthesizable PLL
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019
292019
Transmuter: Bridging the efficiency gap using memory and dataflow reconfiguration
S Pal, S Feng, D Park, S Kim, A Amarnath, CS Yang, X He, J Beaumont, ...
Proceedings of the ACM International Conference on Parallel Architectures …, 2020
272020
A 7.3 m output non-zeros/j sparse matrix-matrix multiplication accelerator using memory reconfiguration in 40 nm
S Pal, D Park, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ...
2019 Symposium on VLSI Technology, C150-C151, 2019
242019
SparseAdapt: Runtime control for sparse linear algebra on a reconfigurable accelerator
S Pal, A Amarnath, S Feng, M O'Boyle, R Dreslinski, C Dubach
MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021
192021
Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm
T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Rao, ...
First Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017
142017
Heterogeneity-aware scheduling on SoCs for autonomous vehicles
A Amarnath, S Pal, HT Kassa, A Vega, A Buyuktosunoglu, H Franke, ...
IEEE Computer Architecture Letters 20 (2), 82-85, 2021
132021
STOMP: A tool for evaluation of scheduling policies in heterogeneous multi-processors
A Vega, A Amarnath, JD Wellman, H Kassa, S Pal, H Franke, ...
arXiv preprint arXiv:2007.14371, 2020
132020
A survey describing beyond Si transistors and exploring their implications for future processors
H Kim, A Amarnath, J Bagherzadeh, N Talati, RG Dreslinski
ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (3), 1-44, 2021
102021
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology
A Amarnath, J Bagherzadeh, J Tan, RG Dreslinski
2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019
82019
A carbon nanotube transistor based RISC-V processor using pass transistor logic
A Amarnath, S Feng, S Pal, T Ajayi, A Rovinski, RG Dreslinski
2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017
82017
STOMP: Agile evaluation of scheduling policies in heterogeneous multi-processors
A Vega, JD Wellman, H Franke, A Buyuktosunoglu, P Bose, A Amarnath, ...
DOSSA-3 Workshop@ HPCA, 2021
62021
Hetsched: Quality-of-mission aware scheduling for autonomous vehicle socs
A Amarnath, S Pal, H Kassa, A Vega, A Buyuktosunoglu, H Franke, ...
arXiv preprint arXiv:2203.13396, 2022
42022
Heterogeneous system on a chip scheduler
A Vega, A Buyuktosunoglu, H Franke, JD Wellman, P Bose, RM Senger, ...
US Patent 11,704,155, 2023
32023
R2D3: A reliability engine for 3D parallel systems
J Bagherzadeh, A Amarnath, J Tan, S Pal, RG Dreslinski
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
22020
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