| Formal verification by symbolic evaluation of partially-ordered trajectories CJH Seger, RE Bryant Formal Methods in System Design 6 (2), 147-189, 1995 | 377 | 1995 |
| Asynchronous circuits JA Brzozowski, CJH Seger Springer Science & Business Media, 1995 | 373 | 1995 |
| Formally verifying IEEE compliance of floating-point hardware J O’Leary, X Zhao, R Gerth, CJH Seger Intel Technology Journal 3 (1), 1-14, 1999 | 166 | 1999 |
| Formal hardware verification by symbolic ternary trajectory evaluation RE Bryant, DL Beatty, CJH Seger Proceedings of the 28th ACM/IEEE Design Automation Conference, 397-402, 1991 | 161 | 1991 |
| An industrially effective environment for formal hardware verification CJH Seger, RB Jones, JW O'Leary, T Melham, MD Aagaard, C Barrett, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 127 | 2005 |
| Vos: A Formal Hardware Verification System User's Guide CJH Seger University of British Columbia. Department of Computer Science, 1993 | 110 | 1993 |
| Formal verification of digital circuits using symbolic ternary system models RE Bryant, CJH Seger Computer-Aided Verification: Proc. of the 2nd International Conference CAV …, 1991 | 110 | 1991 |
| Formal verification using parametric representations of boolean constraints MD Aagaard, RB Jones, CJH Serger Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 402-407, 1999 | 102 | 1999 |
| Linking BDD-based symbolic evaluation to interactive theorem-proving JJ Joyce, CJH Seger Proceedings of the 30th international Design Automation Conference, 469-474, 1993 | 94 | 1993 |
| Introduction to generalized symbolic trajectory evaluation J Yang, CJH Seger IEEE transactions on very large scale integration (VLSI) systems 11 (3), 345-353, 2003 | 93 | 2003 |
| Combining theorem proving and trajectory evaluation in an industrial environment MD Aagaard, RB Jones, CJH Seger Proceedings of the 35th annual Design Automation Conference, 538-541, 1998 | 88 | 1998 |
| The formal verification of a pipelined double-precision IEEE floating-point multiplier MD Aagaard, CJH Seger Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 88 | 1995 |
| Symbolic trajectory evaluation S Hazelhurst, CJH Seger Formal hardware verification: Methods and systems in comparison, 3-78, 2005 | 79 | 2005 |
| A simple theorem prover based on symbolic trajectory evaluation and BDD's S Hazelhurst, CJH Seger IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995 | 78 | 1995 |
| Advances in asynchronous circuit theory. Part I: gate and unbounded inertial delay JA Brzozowski, CJH Seger Bulletin of the European Association for Theoretical Computer Science, EATCS …, 1990 | 77 | 1990 |
| Lifted-fl: A pragmatic implementation of combined model checking and theorem proving MD Aagaard, RB Jones, CJH Seger Theorem Proving in Higher Order Logics: 12th International Conference …, 1999 | 73 | 1999 |
| Generalized symbolic trajectory evaluation—abstraction in action J Yang, CJH Seger Formal Methods in Computer-Aided Design: 4th International Conference, FMCAD …, 2002 | 65 | 2002 |
| Practical formal verification in microprocessor design RB Jones, JW O'Leary, CJH Seger, MD Aagaard, TF Melham IEEE design & test of computers 18 (4), 16-25, 2001 | 65 | 2001 |
| A Methodology for Formal Hardware Verification, with Application to Microprocessors. DL Beatty, RE Bryant, EM Clarke Jr, AL Fisher, CJH Seger CARNEGIE-MELLON UNIV PITTSBURGH PA SCHOOL OF COMPUTER SCIENCE, 1993 | 62 | 1993 |
| The HOL-Voss system: Model-checking inside a general-purpose theorem-prover J Joyce, C Seger Higher Order Logic Theorem Proving and Its Applications: 6th International …, 2005 | 61 | 2005 |
