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Alpa Trivedi
Alpa Trivedi
Research Scientist, Intel Labs
Verified email at intel.com
Title
Cited by
Cited by
Year
Method and system for protecting memory information in a platform
ATN Trivedi, DM Durham, M Long, S Chhabra, UR Savagaonkar, ...
US Patent 9,092,644, 2015
71*2015
Trusted timer service
ATN Trivedi, S Chhabra, KS Grewal, DM Durham
US Patent 10,068,068, 2018
68*2018
Memory integrity with error detection and correction
DM Durham, S Chhabra, S Deutsch, M Long, ATN Trivedi
US Patent 9,990,249, 2018
362018
Creating secure channels between a protected execution environment and fixed-function endpoints
AN Trivedi, S Chhabra, U Savagaonkar, M Long
US Patent 9,852,301, 2017
30*2017
Parallelized counter tree walk for low overhead memory replay protection
S Chhabra, UR Savagaonkar, DM Durham, NL Cooray, M Long, ...
US Patent 8,819,455, 2014
262014
Encryption interface
EM Kishinevsky, UR Savagaonkar, ATN Trivedi, S Chhabra, BV Patel, ...
US Patent 9,614,666, 2017
222017
Entry/exit architecture for protected device modules
X Kang, ATN Trivedi, S Chhabra, P Dewan, UR Savagaonkar, ...
US Patent 9,652,609, 2017
192017
Apparatus, system and method of protecting domains of a multimode wireless radio transceiver
FA Sheikh, P Koeberl, J Walker, H Alavi, M Long, RK Krishnamurthy, ...
US Patent 9,307,409, 2016
172016
Incorporating access control functionality into a system on a chip (SoC)
MR Sastry, IT Schoinas, RJ Toepfer, ATN Trivedi, M Long
US Patent 9,805,221, 2017
152017
Secure environment for graphics processing units
P Dewan, UR Savagaonkar, DM Durham, PS Schmitz, J Martin, ...
US Patent 9,519,803, 2016
152016
Low-overhead cryptographic method and apparatus for providing memory confidentiality, integrity and replay protection
S Chhabra, UR Savagaonkar, CV Rozas, ATN Trivedi, M Long, ...
US Patent 9,053,346, 2015
142015
Article holder adapted for being supported by a fence
LC Roach
US Patent 6,659,412, 2003
142003
Technologies for secure authentication and programming of accelerator devices
V Scarlata, R Lal, AN Trivedi, E Innis
US Patent 11,386,017, 2022
132022
Security plugin for a system-on-a-chip platform
MR Sastry, AN Trivedi, M Long
US Patent 10,726,162, 2020
122020
System, apparatus and method for secure monotonic counter operations in a processor
P Dewan, S Chhabra, DM Durham, KS Grewal, ATN Trivedi
US Patent 10,592,435, 2020
92020
System and method for enabling secure memory transactions using enclaves
AN Trivedi, R Sahita, D Durham, K Grewal, P Dewan, S Chhabra
US Patent 10,565,370, 2020
92020
Techniques to enable scalable cryptographically protected memory using on-chip memory
AN Trivedi, S Chhabra, D Durham
US Patent 10,102,370, 2018
92018
Entry/exit architecture for protected device modules
X Kang, ATN Trivedi, S Chhabra, P Dewan, UR Savagaonkar, ...
US Patent 9,087,202, 2015
92015
Cryptographic protection for trusted operating systems
ATN Trivedi, S Chhabra, DM Durham
US Patent 10,536,274, 2020
82020
Techniques for compression memory coloring
DM Durham, S Deutsch, S Komijani, ATN Trivedi, S Chhabra
US Patent 10,387,305, 2019
82019
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