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Daniele Vogrig
Daniele Vogrig
Ricercatore in ingegneria Elettronica, Università di Padova
Verified email at dei.unipd.it - Homepage
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Year
A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13CMOS
S Solda, M Caruso, A Bevilacqua, A Gerosa, D Vogrig, A Neviani
IEEE Journal of Solid-State Circuits 46 (7), 1636-1647, 2011
942011
An energy-detector for noncoherent impulse-radio UWB receivers
A Gerosa, S Solda, A Bevilacqua, D Vogrig, A Neviani
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (5), 1030-1040, 2009
902009
A 0.35-/spl mu/m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code
D Vogrig, A Gerosa, A Neviani, AG Amat, G Montorsi, S Benedetto
IEEE Journal of Solid-State Circuits 40 (3), 753-762, 2005
832005
Test results and prospects for RD53A, a large scale 65 nm CMOS chip for pixel readout at the HL-LHC
L Gaioni, RD53 Collaboration
Nuclear Instruments and Methods in Physics Research Section A: Accelerators …, 2019
342019
Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC
N Demaria, MB Barbero, D Fougeron, F Gensolen, S Godiot, M Menouni, ...
Journal of Instrumentation 11 (12), C12058, 2016
292016
An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels
A Xotta, D Vogrig, A Gerosa, A Neviani, AG i Amat, G Montorsi, ...
2002 IEEE International Symposium on Circuits and Systems (ISCAS) 5, V-V, 2002
252002
An analog turbo decoder for the UMTS standard
AG i Amat, G Montorsi, S Benedetto, D Vogrig, A Neviani, A Gerosa
International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings., 296, 2004
242004
Design of analog front-ends for the RD53 demonstrator chip
L Gaioni, FE Rarbi, N Demaria, G Della Casa, ML Prydderch, V Kafka, ...
PoS, 036, 2017
92017
Design, simulation, and testing of a CMOS analog decoder for the block length-40 UMTS turbo code
AG i Amat, S Benedetto, G Montorsi, D Vogrig, A Neviani, A Gerosa
IEEE transactions on communications 54 (11), 1973-1982, 2006
92006
Capture and emission time map to investigate the positive VTH shift in p-GaN power HEMTs
N Modolo, M Fregolent, F Masin, A Benato, A Bettini, M Buffolo, ...
Microelectronics Reliability 138, 114708, 2022
82022
RD53A: a large scale prototype for HL-LHC silicon pixel detector phase 2 upgrades
E Monteil, M Barbero, D Fougeron, S Godiot, M Menouni, P Pangaud, ...
POS PROCEEDINGS OF SCIENCE 343, 1-4, 2018
82018
Development of a large pixel chip demonstrator in RD53 for ATLAS and CMS upgrades
E Conti, P Pangaud, P Breugnon, M Menichelli, G De Robertis, S Orfanelli, ...
PoS, 005, 2017
72017
65 nm technology for HEP: Status and perspective
P Valerio, MB Barbero, D Fougeron, F Gensolen, S Godiot, M Menouni, ...
POS PROCEEDINGS OF SCIENCE 15 (September-2014), 1-10, 2014
72014
A digitally programmable ring oscillator in the UWB range
A Gerosa, S Soldà, A Bevilacqua, D Vogrig, A Neviani
Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010
72010
Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC
S Marconi, MB Barbero, D Fougeron, S Godiot, M Menouni, P Pangaud, ...
2018 IEEE Nuclear Science Symposium and Medical Imaging Conference …, 2018
52018
A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request
S Soldà, M Caruso, A Bevilacqua, A Gerosa, D Vogrig, A Neviani
2010 Proceedings of ESSCIRC, 498-501, 2010
52010
Analog decoding of trellis coded modulation for multi-level flash memories
S Solda, D Vogrig, A Bevilacqua, A Gerosa, A Neviani
2008 IEEE International Symposium on Circuits and Systems, 744-747, 2008
52008
RD53 analog front-end processors for the ATLAS and CMS experiments at the High-Luminosity LHC
L Gaioni, M Manghisoni, V Re, E Riceputi, G Traversi, MB Barbero, ...
28th International Workshop on Vertex Detectors (Vertex 2019), 021, 2019
42019
A Symbol-Duty-Cycled 440-pJ/b Impulse Radio Receiver With 0.57-aJ Sensitivity in 130-nm CMOS
D Vogrig, A Bevilacqua, A Gerosa, A Neviani
IEEE Transactions on Microwave Theory and Techniques 65 (2), 565-573, 2016
32016
CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code
AG i Amat, D Vogrig, S Benedetto, G Montorsi, A Neviani, A Gerosa
IEEE Globecom 2006, 1-6, 2006
32006
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