Tutu Ajayi
Tutu Ajayi
E-mail megerősítve itt: umich.edu
Hivatkozott rá
Hivatkozott rá
Toward an open-source digital flow: First learnings from the openroad project
T Ajayi, VA Chhabria, M Fogaça, S Hashemi, A Hosny, AB Kahng, M Kim, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019
The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips
S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ...
IEEE Micro 38 (2), 30-41, 2018
OpenROAD: Toward a self-driving, open-source digital layout implementation tool chain
T Ajayi, D Blaauw
Proceedings of Government Microcircuit Applications and Critical Technology …, 2019
Celerity: An open source RISC-V tiered accelerator fabric
T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ...
Symp. on High Performance Chips (Hot Chips), 2017
An open-source framework for autonomous SoC design with analog block generation
T Ajayi, S Kamineni, YK Cherivirala, M Fayazi, K Kwon, M Saligane, ...
2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration …, 2020
A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
2019 Symposium on VLSI Circuits, C30-C31, 2019
Evaluating celerity: A 16-nm 695 Giga-RISC-V instructions/s manycore processor with synthesizable PLL
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019
Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm
First Workshop on Computer Architecture Research with RISC-V (CARRV), 2017
Versa: A 36-core systolic multiprocessor with dynamically reconfigurable interconnect and memory
S Kim, M Fayazi, A Daftardar, KY Chen, J Tan, S Pal, T Ajayi, Y Xiong, ...
IEEE Journal of Solid-State Circuits 57 (4), 986-998, 2022
Bridging academic open-source EDA to real-world usability
A Rovinski, T Ajayi, M Kim, G Wang, M Saligane
Proceedings of the 39th International Conference on Computer-Aided Design, 1-7, 2020
A carbon nanotube transistor based RISC-V processor using pass transistor logic
A Amarnath, S Feng, S Pal, T Ajayi, A Rovinski, RG Dreslinski
2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017
Versa: A dataflow-centric multiprocessor with 36 systolic arm cortex-m4f cores and a reconfigurable crossbar-memory hierarchy in 28nm
S Kim, M Fayazi, A Daftardar, KY Chen, J Tan, S Pal, T Ajayi, Y Xiong, ...
2021 Symposium on VLSI Circuits, 1-2, 2021
A unified forward error correction accelerator for multi-mode Turbo, LDPC, and polar decoding
Y Yue, T Ajayi, X Liu, P Xing, Z Wang, D Blaauw, R Dreslinski, HS Kim
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2022
Fully autonomous mixed signal SoC design & layout generation platform
T Ajayi, Y Cherivirala, K Kwon, S Kamineni, M Saligane, M Fayazi, ...
IEEE, 2020
FASCINET: A fully automated single-board computer generator using neural networks
M Fayazi, Z Colter, Z Benameur-El Youbi, J Bagherzadeh, T Ajayi, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022
Enabling software-defined rf convergence with a novel coarse-scale heterogeneous processor
DW Bliss, T Ajayi, A Akoglu, I Aliyev, T Basaklar, L Belayneh, D Blaauw, ...
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 443-447, 2022
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation
T Ajayi, S Kamineni, M Fayazi, YK Cherivirala, K Kwon, S Gupta, W Duan, ...
VLSI-SoC: Design Trends: 28th IFIP WG 10.5/IEEE International Conference on …, 2021
A 33.06 Gb/s Reconfigurable Galois Field oFEC Decoder for Optical Inter-Satellite Communication
X Wei, Y Yue, S Choi, T Ajayi, R Dreslinski, D Blaauw, HS Kim
Authorea Preprints, 2024
A Fully Configurable Unified FEC Decoder for LDPC, Polar, Turbo, and Convolutional Codes with Row-First Collision-Free Compression
Y Yue, S Choi, T Ajayi, X Wei, R Dreslinski, D Blaauw, HS Kim
Authorea Preprints, 2024
FALCON: An FPGA Emulation Platform for Domain-Specific Systems-on-Chip (DSSoCs)
A Krishnakumar, H Yu, T Ajayi, AA Goksoy, V Pandey, J Mack, S Hassan, ...
IEEE Design & Test, 2023
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