Követés
Syed Ershad Ahmed
Syed Ershad Ahmed
BITS Pilani Hyderabad Campus
E-mail megerősítve itt: hyderabad.bits-pilani.ac.in - Kezdőlap
Cím
Hivatkozott rá
Hivatkozott rá
Év
Low-power compressor-based approximate multipliers with error correcting module
UA Kumar, SK Chatterjee, SE Ahmed
IEEE Embedded Systems Letters 14 (2), 59-62, 2021
262021
Design of prefix-based optimal reversible comparator
C Vudadha, PS Phaneendra, V Sreehari, SE Ahmed, NM Muthukrishnan, ...
2012 IEEE Computer Society Annual Symposium on VLSI, 201-206, 2012
262012
Low-power self reconfigurable multiplexer based decoder for adaptive resolution flash adcs
C Vudadha, G Makkena, MVS Nayudu, PS Phaneendra, SE Ahmed, ...
2012 25th International Conference on VLSI Design, 280-285, 2012
232012
An iterative logarithmic multiplier with improved precision
SE Ahmed, S Kadam, MB Srinivas
2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH), 104-111, 2016
222016
An improved logarithmic multiplier for media processing
SE Ahmed, MB Srinivas
Journal of Signal Processing Systems 91, 561-574, 2019
182019
DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications
S Nambi, UA Kumar, K Radhakrishnan, M Venkatesan, SE Ahmed
IEEE Embedded Systems Letters 13 (4), 174-177, 2020
172020
A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits
S Ganguly, A Mittal, SE Ahmed, MB Srinivas
2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 69-72, 2014
152014
Improved designs of digit-by-digit decimal multiplier
SE Ahmed, S Varma, MB Srinivas
Integration 61, 150-159, 2018
122018
A modified twin precision multiplier with 2D bypassing technique
SE Ahmed, S Abraham, S Veeramanchaneni, MB Srinivas
2012 International Symposium on Electronic System Design (ISED), 102-106, 2012
122012
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders
C Vudadha, PS Phaneendra, SE Ahmed, V Sreehari, NM Muthukrishnan, ...
2012 IEEE Computer Society Annual Symposium on VLSI, 225-230, 2012
82012
A reconfigurable INC/DEC/2's complement/priority encoder circuit with improved decision block
VC Kumar, PS Phaneendra, SE Ahmed, V Sreehari, NM Muthukrishnan, ...
2011 International Symposium on Electronic System Design, 100-105, 2011
72011
A unified architecture for BCD and binary adder/subtractor
VC Kumar, PS Phaneendra, SE Ahmed, S Veeramachaneni, ...
2011 14th Euromicro Conference on Digital System Design, 426-429, 2011
72011
An Area and Delay Efficient Logarithmic Multiplier
N Alla, SE Ahmed
2020 International Conference on Contemporary Computing and Applications …, 2020
62020
A reconfigurable parallel prefix ling adder with modified enhanced flagged binary logic
S Ganguly, A Mittal, SE Ahmed
2012 Asia Pacific Conference on Postgraduate Research in Microelectronics …, 2012
62012
Compressor based hybrid approximate multiplier architectures with efficient error correction logic
AK Uppugunduru, SV Bharadwaj, SE Ahmed
Computers and Electrical Engineering 104, 108407, 2022
52022
Hardware-efficient approximate multiplier architectures for media processing applications
AK Uppugunduru, SE Ahmed
Circuit World 48 (2), 223-232, 2022
52022
A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications
UA Kumar, G Sahith, SK Chatterjee, SE Ahmed
Journal of Circuits, Systems and Computers 31 (03), 2250049, 2022
52022
A prefix based reconfigurable adder
C Kumar, SE Ahmed, S Veeramachaneni, NM Muthukrishnan, ...
2011 IEEE Computer Society Annual Symposium on VLSI, 349-350, 2011
52011
Design methodology for highly accurate approximate multipliers for error resilient applications
S Guturu, UA Kumar, SV Bharadwaj, SE Ahmed
Computers and Electrical Engineering 110, 108798, 2023
42023
Approximate Multiplier Architectures for Error Resilient Applications
UA Kumar, RK Chintakunta, S Kumar, K Jamal, SE Ahmed
2021 IEEE International Symposium on Smart Electronic Systems (iSES), 89-92, 2021
42021
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Cikkek 1–20