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Amir Nahir
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A unified methodology for pre-silicon verification and post-silicon validation
A Adir, S Copty, S Landa, A Nahir, G Shurek, A Ziv, C Meissner, ...
2011 Design, Automation & Test in Europe, 1-6, 2011
872011
Bridging pre-silicon verification and post-silicon validation
A Nahir, A Ziv, R Galivanche, A Hu, M Abramovici, A Camilleri, B Bentley, ...
Proceedings of the 47th Design Automation Conference, 94-95, 2010
552010
Threadmill: A post-silicon exerciser for multi-threaded processors
A Adir, M Golubev, S Landa, A Nahir, G Shurek, V Sokhin, A Ziv
Proceedings of the 48th Design Automation Conference, 860-865, 2011
502011
Reaching coverage closure in post-silicon validation
A Adir, A Nahir, A Ziv, C Meissner, J Schumann
Hardware and Software: Verification and Testing: 6th International Haifa …, 2011
482011
Replication-based load balancing
A Nahir, A Orda, D Raz
IEEE Transactions on Parallel and Distributed Systems 27 (2), 494-507, 2015
392015
On cost-aware monitoring for self-adaptive load sharing
D Breitgand, R Cohen, A Nahir, D Raz
IEEE Journal on Selected Areas in communications 28 (1), 70-83, 2009
392009
Topology design and control: A game-theoretic perspective
A Nahir, A Orda, A Freund
IEEE INFOCOM 2009, 1620-1628, 2009
322009
Post-silicon validation of the IBM POWER8 processor
A Nahir, M Dusanapudi, S Kapoor, K Reick, W Roesner, KD Schubert, ...
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
302014
Topology design of communication networks: A game-theoretic perspective
A Nahir, A Orda, A Freund
IEEE/ACM Transactions on Networking 22 (2), 405-414, 2013
282013
Workload factoring with the cloud: A game-theoretic perspective
A Nahir, A Orda, D Raz
2012 Proceedings IEEE INFOCOM, 2566-2570, 2012
282012
TAB-BackSpace: Unlimited-length trace buffers with zero additional on-chip overhead
FM de Paula, A Nahir, Z Nevo, A Orni, AJ Hu
Proceedings of the 48th Design Automation Conference, 411-416, 2011
272011
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor
A Adir, A Nahir, G Shurek, A Ziv, C Meissner, J Schumann
Proceedings of the 48th Design Automation Conference, 569-574, 2011
252011
Dynamic selection of trace signals for post-silicon debug
K Basu, P Mishra, P Patra, A Nahir, A Adir
2013 14th International Workshop on Microprocessor Test and Verification, 62-67, 2013
242013
Verification of transactional memory in power8
A Adir, D Goodman, D Hershcovich, O Hershkovitz, B Hickerson, K Holtz, ...
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
222014
Hardware verification using acceleration platform
M Dusanapudi, W Kadry, S Kapoor, D Krestyashyn, S Landa, A Nahir, ...
US Patent 8,832,502, 2014
182014
Control flow error localization
O Friedler, W Kadry, A Nahir, V Sokhin
US Patent 9,251,045, 2016
152016
nuTAB-BackSpace: Rewriting to normalize non-determinism in post-silicon debug traces
FM De Paula, AJ Hu, A Nahir
Computer Aided Verification: 24th International Conference, CAV 2012 …, 2012
152012
Resource allocation and management in cloud computing
A Nahir, A Orda, D Raz
2015 IFIP/IEEE International Symposium on Integrated Network Management (IM …, 2015
142015
Optimizing test-generation to the execution platform
A Nahir, A Ziv, S Panda
17th Asia and South Pacific Design Automation Conference, 304-309, 2012
142012
Schedule first, manage later: Network-aware load balancing
A Nahir, A Orda, D Raz
2013 Proceedings IEEE INFOCOM, 510-514, 2013
122013
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Articles 1–20