| GemDroid: A framework to evaluate mobile platforms N Chidambaram Nachiappan, P Yedlapalli, N Soundararajan, ... ACM SIGMETRICS Performance Evaluation Review 42 (1), 355-366, 2014 | 51 | 2014 |
| Improving bank-level parallelism for irregular applications X Tang, M Kandemir, P Yedlapalli, J Kotra 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016 | 48 | 2016 |
| Domain knowledge based energy management in handhelds NC Nachiappan, P Yedlapalli, N Soundararajan, A Sivasubramaniam, ... 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 46 | 2015 |
| Meeting midway: Improving CMP performance with memory-side prefetching P Yedlapalli, J Kotra, E Kultursay, M Kandemir, CR Das, ... Proceedings of the 22nd International Conference on Parallel Architectures …, 2013 | 42 | 2013 |
| Page compressibility checker F Guo, P Yedlapalli US Patent 9,600,317, 2017 | 27 | 2017 |
| Short-circuiting memory traffic in handheld platforms P Yedlapalli, NC Nachiappan, N Soundararajan, A Sivasubramaniam, ... 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 166-177, 2014 | 27 | 2014 |
| A special-purpose compiler for look-up table and code generation for function evaluation Y Zhang, L Deng, P Yedlapalli, SP Muralidhara, H Zhao, M Kandemir, ... 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 25 | 2010 |
| Locality-aware mapping and scheduling for multicores W Ding, Y Zhang, M Kandemir, J Srinivas, P Yedlapalli Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation …, 2013 | 20 | 2013 |
| Content-based swap candidate selection F Guo, P Yedlapalli US Patent 9,342,344, 2016 | 14 | 2016 |
| Trading cache hit rate for memory performance W Ding, M Kandemir, D Guttman, A Jog, CR Das, P Yedlapalli Proceedings of the 23rd international conference on Parallel architectures …, 2014 | 9 | 2014 |
| Efficient handling of block write atomicity T Kiran, R Venkatasubramanian, X Deguillard, P Yedlapalli US Patent 10,936,446, 2021 | 5 | 2021 |
| Cache hierarchy-aware query mapping on emerging multicore architectures O Ozturk, U Orhan, W Ding, P Yedlapalli, MT Kandemir IEEE Transactions on Computers 66 (3), 403-415, 2016 | 4 | 2016 |
| QoS Aware Dynamic Time-Slice Tuning Y Ding, P Yedlapalli, M Kandemir | 4 | 2014 |
| A cache topology-aware multi-query scheduler for multicore architectures U Orhan, W Ding, P Yedlapalli, M Kandemir, O Ozturk 2014 IEEE International Symposium on Workload Characterization (IISWC), 86-87, 2014 | 3 | 2014 |
| Cooperative parallelization P Yedlapalli, E Kultursay, MT Kandemir 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 134-141, 2011 | 3 | 2011 |
| Visual Search Optimization P Thinakaran, D Guttman, MT Kandemir, M Arunachalam, R Khanna, ... High Performance Parallelism Pearls: Multicore and Many-core Programming …, 2015 | 2 | 2015 |
| A study of parallelism-locality tradeoffs across memory hierarchy P Yedlapalli The Pennsylvania State University, 2015 | | 2015 |
Mahmut KandemirPennsylvania State UniversityVerified email at psu.edu
