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Ragh Kuttappa
Ragh Kuttappa
Research Scientist, Intel Labs
Verified email at drexel.edu
Title
Cited by
Cited by
Year
Snacknoc: Processing in the communication layer
K Sangaiah, M Lui, R Kuttappa, B Taskin, M Hempstead
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
132020
Resonant clock synchronization with active silicon interposer for multi-die systems
R Kuttappa, B Taskin, S Lerner, V Pano
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (4), 1636-1645, 2021
112021
3D NoCs with active interposer for multi-die systems
V Pano, R Kuttappa, B Taskin
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip …, 2019
92019
RotaSYN: Rotary traveling wave oscillator SYNthesizer
R Kuttappa, A Balaji, V Pano, B Taskin, H Mahmoodi
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (7), 2685-2698, 2019
92019
Robust low power clock synchronization for multi-die systems
R Kuttappa, B Taskin, S Lerner, V Pano, I Savidis
2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019
72019
Stability of rotary traveling wave oscillators under process variations and NBTI
R Kuttappa, L Filippini, S Lerner, B Taskin
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
72017
Low frequency rotary traveling wave oscillators
R Kuttappa, B Taskin
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
62018
Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging
R Kuttappa, H Homayoun, H Salmani, H Mahmoodi
Microelectronics Reliability 62, 156-166, 2016
52016
Comprehensive low power adiabatic circuit design with resonant power clocking
R Kuttappa, S Khoa, L Filippini, V Pano, B Taskin
2020 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2020
32020
Distributed digital low-dropout regulators with phase interleaving for on-chip voltage noise mitigation
L Wang, R Kuttappa, B Taskin, S Köse
2019 ACM/IEEE International Workshop on System Level Interconnect Prediction …, 2019
32019
Reconfigurable threshold logic gates using optoelectronic capacitors
R Kuttappa, L Khuon, B Nabet, B Taskin
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
32017
FOPAC: Flexible On-Chip Power and Clock
R Kuttappa, S Köse, B Taskin
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (12), 4628-4636, 2019
22019
Scalable resonant power clock generation for adiabatic logic design
R Kuttappa, L Filippini, N Sica, B Taskin
2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 338-342, 2021
12021
Low Swing—Low Frequency Rotary Traveling Wave Oscillators
R Kuttappa, S Lerner, L Filippini, B Taskin
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
12019
Comparative analysis of robustness of spin transfer torque based look up tables under process variations
R Kuttappa, H Homayoun, H Salmani, H Mahmoodi
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 606-609, 2016
12016
INTEGRATED CIRCUIT STRUCTURES HAVING MAGNETIC VIAS AND BACKSIDE POWER DELIVERY
R Kuttappa, T Karnik, MD Pant
US Patent App. 17/894,868, 2024
2024
Resonant rotary clocking for synchronized clock signals
V Honkote, R Kuttappa, S Yada, T Karnik, DJ Kurian, JS Priya
US Patent App. 17/558,515, 2023
2023
A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators
R Kuttappa, B Taskin
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 687-691, 2022
2022
Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer
R Kuttappa, B Taskin, V Honkote, S Yada, J Sundaram, D Kurian, T Karnik, ...
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 692-696, 2022
2022
Flexible on-chip power and clock
B Taskin, R Kuttappa, S Kose
US Patent 11,243,559, 2022
2022
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